ACS8510 Rev2.1 SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements ADVANCED COMMUNICATIONS Description FINAL Features The ACS8510 Rev2.1 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and Frame Synchronization clocks. The ACS8510 Rev2.1 is fully compliant with the required international specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 Rev2.1 generates independent SEC and BITS/SSU clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 Rev2.1 devices can be used together in a Master/ Slave configuration mode allowing system protection against a single ACS8510 Rev2.1 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. The User can choose between OCXO or TCXO to define the Stratum and/or Holdover performance required. Block Diagram DATASHEET Suitable for Stratum 3E*, 3, 4E, 4 and SONET Minimum Clock (SMC) or SONET/SDH Equipment Clock (SEC) applications Meets AT&T, ITU-T, ETSI and Telcordia specifications Accepts 14 individual input reference clocks Generates eleven output clocks Supports Free-run, Locked and Holdover modes of operation Robust input clock source quality monitoring on all inputs Automatic "hit-less" source switchover on loss of input Phase build-out for output clock phase continuity during input switchover and mode transitions Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz Support for Master/Slave device configuration alignment and hot/standby redundancy IEEE 1149.1 JTAG Boundary Scan Single +3.3 V operation, +5 V I/O compatible Operating temperature (ambient) -40C to +85C Available in 100 pin LQFP package Lead (Pb)-free version available (ACS8510 Rev2.1T), RoHS and WEEE compliant. Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz Figure 1 Block Diagram of the ACS8510 Rev2.1 SETS Programmable Outputs: TO1 (TTL/CMOS) = 6.48 MHz (default) 19.44 MHz and 25.92 MHz, and E1/DS1 multiples: 1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz) T4 DPLL/Freq. Synthesis 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8 kHz (AMI) 2 kHz 4 kHz N x 8 kHz 1.544/2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz TOUT4 Selector Divider PFD Digital Loop Filter TO2 (TTL/CMOS) = 38.88 MHz (default) 25.92 MHz, 51.84 MHz, and E1/DS1 multiples: 1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz) DTO Input Port Monitors and Selection Control TO3 (TTL/CMOS) = 19.44 MHz (fixed) TO4 (TTL/CMOS) = 38.88 MHz (fixed) 11 x Output Ports T0 DPLL/Freq. Synthesis 14 x SEC TOUT0 Selecor Divider PFD Digital Loop Filter T0 APLL (output) DTO Frequency Dividers TO5 (TTL/CMOS) = 77.76 MHz (fixed) TO6 (LVDS (default)/PECL) = 38.88 MHz (default) 19.44 MHz , 155.52 MHz (OC-3), 311.04 MHz, and E1/DS1 multiples: 1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz) TO7 (PECL (default)/LVDS) = Programmable: 19.44 MHz (default), 51.84 MHz (OC-1), 77.76 MHz and 155.52 MHz (OC-3) T08 (AMI) = 64/8 kHz (composite clock 64 kHz + 8 kHz) TCK TDI TMS TRST TDO TO9 (TTL/CMOS) = IEEE 1149.1 JTAG Chip Clock Generator 1.544 MHz/2.048 MHz (E1/DS1) Priority Register Set Table Microprocessor Port FrSync (TO10) (TTL/CMOS) = 8 kHz Frame Sync, Fixed 50:50 MSR MFrSync (TO11) (TTL/CMOS) = 2 kHz Multiframe Sync, Fixed 50:50 MSR OCXO or TCXO F8510D_001BLOCKDIA_01 Revision 2.02/June 2006 (c) Semtech Corp. Page 1 www.semtech.com Table of Contents ADVANCED COMMUNICATIONS Table of Contents FINAL Section ACS8510 Rev2.1 SETS DATASHEET Page Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Description........................................................................................................................................................................................... 5 Functional Description .............................................................................................................................................................................. 8 Local Oscillator Clock.........................................................................................................................................................................8 Crystal Frequency Calibration.................................................................................................................................................. 9 Input Interfaces..................................................................................................................................................................................9 Over-Voltage Protection .....................................................................................................................................................................9 Input Reference Clock Ports .............................................................................................................................................................9 DivN Examples....................................................................................................................................................................... 11 Input Wander and Jitter Tolerance ................................................................................................................................................ 12 Frame Sync and MultiFrame Sync Clocks (Part of TOUT0) .................................................................................................. 13 Output Clock Ports .......................................................................................................................................................................... 13 Low-speed Output Clock (TOUT4) .......................................................................................................................................... 13 High-speed Output Clock (Part of TOUT0) ............................................................................................................................. 13 Low Jitter Multiple E1/DS1 Outputs .................................................................................................................................... 14 Output Wander and Jitter ............................................................................................................................................................... 14 Phase Variation ............................................................................................................................................................................... 16 Phase Build-Out .............................................................................................................................................................................. 18 Microprocessor Interface ............................................................................................................................................................... 19 Motorola Mode ...................................................................................................................................................................... 19 Intel Mode.............................................................................................................................................................................. 19 Multiplexed Mode.................................................................................................................................................................. 19 Serial Mode............................................................................................................................................................................ 19 EPROM Mode......................................................................................................................................................................... 19 Register Set ..................................................................................................................................................................................... 19 Configuration Registers ........................................................................................................................................................ 19 Status Registers .................................................................................................................................................................... 19 Register Access............................................................................................................................................................................... 19 Interrupt Enable and Clear ............................................................................................................................................................. 20 Register Map ................................................................................................................................................................................... 20 Register Map Description............................................................................................................................................................... 25 Selection of Input Reference Clock Source................................................................................................................................... 39 Forced Control Selection....................................................................................................................................................... 39 Automatic Control Selection ................................................................................................................................................. 39 Ultra Fast Switching .............................................................................................................................................................. 40 External Protection Switching............................................................................................................................................... 40 Clock Quality Monitoring................................................................................................................................................................. 40 Activity Monitoring........................................................................................................................................................................... 42 Frequency Monitoring..................................................................................................................................................................... 42 Modes of Operation ........................................................................................................................................................................ 43 Free-run mode ....................................................................................................................................................................... 43 Pre-Locked mode .................................................................................................................................................................. 43 Locked mode ......................................................................................................................................................................... 43 Lost_Phase mode.................................................................................................................................................................. 43 Holdover mode ...................................................................................................................................................................... 43 Pre-Locked(2) mode.............................................................................................................................................................. 44 Revision 2.02/June 2006 (c) Semtech Corp. Page 2 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Section Page Protection Facility............................................................................................................................................................................ 44 Alignment of Priority Tables in Master and Slave ACS8510 Rev2.1 ................................................................................. 45 Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 Rev2.1 ... 46 Alignment of the Phases of the 8 kHz and 2 kHz Clocks in both Master and Slave ACS8510 Rev2.1 .......................... 46 JTAG ................................................................................................................................................................................................. 46 PORB................................................................................................................................................................................................ 46 Electrical Specification ........................................................................................................................................................................... 49 Operating Conditions ...................................................................................................................................................................... 49 DC Characteristics .......................................................................................................................................................................... 49 DC Characteristics: AMI Input/Output Port ......................................................................................................................... 53 Notes for Tables 25 to 31..................................................................................................................................................... 58 Input/Output Timing ....................................................................................................................................................................... 59 Motorola Mode ...................................................................................................................................................................... 60 Intel Mode.............................................................................................................................................................................. 62 Multiplexed Mode.................................................................................................................................................................. 64 Serial Mode............................................................................................................................................................................ 66 EPROM Mode......................................................................................................................................................................... 68 Package Information .............................................................................................................................................................................. 69 Thermal Conditions......................................................................................................................................................................... 69 Application Information .......................................................................................................................................................................... 71 References .............................................................................................................................................................................................. 72 Abbreviations .......................................................................................................................................................................................... 72 Trademark Acknowledgements ............................................................................................................................................................. 73 Revision Status/History ......................................................................................................................................................................... 74 Notes ....................................................................................................................................................................................................... 75 Ordering Information .............................................................................................................................................................................. 76 Disclaimers...................................................................................................................................................................................... 76 Contact Information for Semtech International AG.............................................................................................................................. 76 Revision 2.02/June 2006 (c) Semtech Corp. Page 3 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Pin Diagram FINAL DATASHEET 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SONSDHB MSTSLVB IC IC IC TO9 TO5 TO4 DGND VDD TO3 TO2 TO1 DGND VDD VDD DGND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Figure 2 ACS8510 Rev2.1 Pin Diagram Synchronous Equipment Timing Source for SONET or SDH Network Elements AGND TRST IC NC AGND VA1+ TMS INTREQ TCK REFCLK DGND VD+ VD+ DGND DGND VD+ NC SRCSW VA2+ AGND TDO IC TDI I1 I2 ACS8510 SONET/SDH SETS Rev 2.1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGND VDD UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFF VDD_DIFF TO6POS TO6NEG TO7POS TO7NEG GND_DIFF VDD_DIFF I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGND VDD 1 2 3 4 5 6 7 8 9 10 11 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Revision 2.02/June 2006 (c) Semtech Corp. Page 4 F8510v21D_002PINDIAG_01 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Pin Description FINAL DATASHEET Table 1 Power Pins Pin Number Symbol I/O Type Description 12, 13, 16 VD+ P - Supply Voltage: Digital supply to gates in analog section, +3.3 Volts 10%. 26 VAMI+ P - Supply Voltage: Digital supply to AMI output, +3.3 Volts 10%. 33, 39 VDD_DIFF P - Supply Voltage: Digital supply for differential ports, +3.3 Volts 10%. 44 VDD5 P - Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. 50, 61, 85, 86 91 VDD P - Supply Voltage: Digital supply to logic, +3.3 Volts 10%. 6 VA1+ P - Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts 10%. 19 VA2+ P - Supply Voltage: Analog supply to output PLLs, +3.3 Volts 10%. 11, 14, 15, 49, 62, 84, 87, 92 DGND P - Supply Ground: Digital ground for logic 29 GND_AMI P - Supply Ground: Digital ground for AMI output. 32, 38 GND_DIFF P - Supply Ground: Digital ground for differential ports. 1, 5, 20 AGND P - Supply Ground: Analog grounds. Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor. Table 2 Not Connected or Internally Connected Pins Pin Number Symbol I/O Type Description 4, 17 NC NC - Not connected: Leave to Float 3, 22, 96, 97, 98 IC IC - Internally Connected: Leave to Float. Revision 2.02/June 2006 (c) Semtech Corp. Page 5 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 3 Other Pins Pin Number Symbol I/O Type Description 2 TRST I TTLD JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for Boundary Scan stand-by mode, still allowing correct device operation. If not used connect to GND or leave floating. 7 TMS I TTLU JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. 8 INTREQ O TTL/CMOS 9 TCK I TTLD JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave floating. This pin may require a capacitor placed between the pin and the nearest GND, to reduce noise pickup. A value of 10 pF should be adequate, but the value is dependent on PCB layout. 10 REFCLK I TTL Reference Clock: 12.800 MHz (refer to "Local Oscillator Clock" on page 8). 18 SRCSW I TTLD Source Switching: Force Fast Source Switching. 21 TDO O TTL/CMOS JTAG Output: Serial test data output. Updated on falling edge of TCK. If not used leave floating. 23 TDI I TTLU JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If not used connect to VDD or leave floating. 24 I1 I AMI Input Reference 1: Composite clock 64 kHz + 8 kHz. 25 I2 I AMI Input Reference 2: Composite clock 64 kHz + 8 kHz. 27 TO8NEG O AMI Output Reference 8: Composite clock, 64 kHz + 8 kHz negative pulse. 28 TO8POS O AMI Output Reference 8: Composite clock, 64 kHz + 8 kHz positive pulse. 30 FrSync O TTL/CMOS Output Reference 10: 8 kHz Frame Sync output (square wave). 31 MFrSync O TTL/CMOS Output Reference 11: 2 kHz Multi-Frame Sync output (square wave). 34, 35 TO6POS, TO6NEG O LVDS/PECL Output Reference 6: Programmable, default 38.88 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04 MHz. Default type LVDS. 36, 37 TO7POS, TO7NEG O PECL/LVDS Output Reference 7: Programmable, default 19.44 MHz, Also 51.84 Also 51.84 MHz, 77.76 MHz, 155.52 MHz. MHz, 77.76 MHz, 155.52 MHz. default type PECL. 40, 41 I5POS, I5NEG I LVDS/PECL Input Reference 5: Default 19.44 MHz, default type LVDS. 42, 43 I6POS, I6NEG I PECL/LVDS Input Reference 6: Default 19.44 MHz, default type PECL. 45 SYNC2K I TTLD Synchronize 2 kHz: Connect to 2 kHz Multi-Frame Sync output of partner ACS8510 Rev2.1 in redundancy system. 46 I3 I TTLD Input Reference 3: Programmable, default 8 kHz. 47 I4 I TTLD Input Reference 4: Programmable, default 8 kHz. 48 I7 I TTLD Input Reference 7: Programmable, default 19.44 MHz. 51 I8 I TTLD Input Reference 8: Programmable, default 19.44 MHz. Revision 2.02/June 2006 (c) Semtech Corp. Interrupt Request: Active High software Interrupt output. Page 6 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 3 Other Pins (cont...) Pin Number Symbol I/O Type Description 52 I9 I TTLD Input Reference 9: Programmable, default 19.44 MHz. 53 I10 I TTLD Input Reference 10: Programmable, default 19.44 MHz. 54 I11 I TTLD Input Reference 11: Programmable, default (Master mode) 1.544/2.048 MHz, default (Slave mode) 6.48 MHz. 55 I12 I TTLD Input Reference 12: Programmable, default 1.544/2.048 MHz. 56 I13 I TTLD Input Reference 13: Programmable, default 1.544/2.048 MHz. 57 I14 I TTLD Input Reference 14: Programmable, default 1.544/2.048 MHz. 58 - 60 UPSEL(2:0) I TTLD Microprocessor Select: Configures the interface for a particular microprocessor type at reset. 63 - 69 A(6:0) I TTLD Microprocessor Interface Address: Address bus for the microprocessor interface registers. A(0) is SDI in Serial mode - output in EPROM mode only. 70 CSB I TTLU Chip Select (Active Low): This pin is asserted Low by the microprocessor to enable the microprocessor interface - output in EPROM mode only. 71 WRB I TTLU Write (Active Low): This pin is asserted Low by the microprocessor to initiate a write cycle. In Motorola mode, WRB = 1 for Read. 72 RDB I TTLU Read (Active Low): This pin is asserted Low by the microprocessor to initiate a read cycle. 73 ALE I TTLD Address Latch Enable: This pin becomes the address latch enable from the microprocessor. When this pin transitions from High to Low, the address bus inputs are latched into the internal registers. ALE = SCLK in Serial mode. 74 PORB I TTLU Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset back to default values. 75 RDY O TTL/CMOS 76 - 83 AD(7:0) IO TTLD 88 TO1 O TTL/CMOS Output Reference 1: Programmable, default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz 89 TO2 O TTL/CMOS Output Reference 2: Programmable, default 38.88 MHz. Also Dig2 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz 90 TO3 O TTL/CMOS Output Reference 3: 19.44 MHz - fixed. 93 TO4 O TTL/CMOS Output Reference 4: 38.88 MHz - fixed. 94 TO5 O TTL/CMOS Output Reference 5: 77.76 MHz - fixed. 95 TO9 O TTL/CMOS Output Reference 9: 1.544/2.048 MHz, as per ITU G.783[9] BITS requirements. 99 MSTSLVB I TTLU Revision 2.02/June 2006 (c) Semtech Corp. Ready/Data Acknowledge: This pin is asserted High to indicate the device has completed a read or write operation. Address/Data: Multiplexed data/address bus depending on the microprocessor mode selection. AD(0) is SDO in Serial mode. Master/Slave Select: Sets the initial power up state (or state after a PORB) of the Master/Slave selection register. The register state can be changed after power up by software. Page 7 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 3 Other Pins (cont...) Pin Number 100 Symbol SONSDHB I/O Type I TTLD Description SONET or SDH Frequency Select: Sets the initial power-up state (or state after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and Reg. 38, Bit 5 and Bit 6. When set Low, SDH rates are selected (2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz etc.) The register states can be changed after power-up by software. Functional Description The ACS8510 Rev2.1 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8510 Rev2.1 generates a stable, low noise clock signal from an internal oscillator. In Locked mode, the ACS8510 Rev2.1 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8510 Rev2.1 generates a stable, low-noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.812, G.813, G.823, and GR-1244-CORE. The ACS8510 Rev2.1 supports all three types of reference clock source: recovered line clock (TIN1), PDH network synchronization timing (TIN2) and node synchronization (TIN3). The ACS8510 Rev2.1 generates independent TOUT0 and TOUT4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. The ACS8510 Rev2.1 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8510 Rev2.1 supports protection. Two ACS8510 Rev2.1 devices can be configured to provide protection against a single ACS8510 Rev2.1 failure. The protection maintains alignment of the two ACS8510 Rev2.1 devices (Master and Slave) and ensures that both ACS8510 Rev2.1 devices maintain the same priority table, choose the same reference input and generate the TOUT0 clock, the 8 kHz Frame Revision 2.02/June 2006 (c) Semtech Corp. Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8510 Rev2.1 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator Clock The Master system clock on the ACS8510 Rev2.1 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperature related parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70C. Table 4 ITU and ETSI Specification Parameter Value Tolerance 4.6 ppm over 20 year lifetime Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) 0.05 ppm/15 seconds @ constant temp. 0.01 ppm/day @ constant temp. 1 ppm over temp. range 0 to +70C Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50C. Table 5 Telcordia GR-1244 CORE Specification Parameter Tolerance Page 8 Value 4.6 ppm over 20 year lifetime www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Table 5 Telcordia GR-1244 CORE Specification Drift (Frequency Drift over supply voltage range of +2.7 V to +3.3 V) FINAL Input Reference Clock Ports DATASHEET Table 6 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pinselectable using the SONSDHB pin). Specific frequencies and priorities are set by configuration. 0.05 ppm/15 seconds @ constant temp. 0.04 ppm/15 seconds @ constant temp. 0.28 ppm/over temp. range 0 to +50C Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8-bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. Although each input port is shown as belonging to one of the types, TIN1, TIN2 or TIN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are: For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be: * 2 kHz 39321 - (5 / 0.02) = 39071 (decimal) * 1.544 MHz (SONET)/2.048 MHz (SDH) * 4 kHz * 8 kHz (and N x 8 kHz) * 6.48 MHz, Input Interfaces * 19.44 MHz, The ACS8510 Rev2.1 supports up to fourteen input reference clock sources from input types TIN1, TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and AMI buffer I/O technologies. These interface technologies support +3.3 V and +5 V operation. * 25.92 MHz, * 38.88 MHz, * 51.84 MHz, * 77.76 MHz. Over-Voltage Protection The ACS8510 Rev2.1 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book). Revision 2.02/June 2006 (c) Semtech Corp. The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, e.g. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilize an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: Page 9 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the lock8K bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8 kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the DivN feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. DATASHEET The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<214-1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the input frequency. When using the DivN feature the post-divider frequency must be 8 kHz, which is indicated by setting the lock8k bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (If the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz. Table 6 Input Reference Source Selection and Priority Table Port Number Channel Number (Bin) Port Type Input Port Technology Frequencies Supported Default Priority I_1 0001 TIN3 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 2 I_2 0010 TIN3 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz 3 I_3 0011 TIN3 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 4 I_4 0100 TIN3 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 8 kHz Default (SDH): 8 kHz 5 I_5 0101 TIN1 LVDS/PECL LVDS Up to 155.52 MHz (see Note (ii)) default Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 6 I_6 0110 TIN1 PECL/LVDS PECL Up to 155.52 MHz (see Note (ii)) default Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 7 I_7 0111 TIN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 8 I_8 1000 TIN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 9 Revision 2.02/June 2006 (c) Semtech Corp. Page 10 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 6 Input Reference Source Selection and Priority Table (cont...) Port Number Channel Number (Bin) Port Type Input Port Technology Frequencies Supported Default Priority I_9 1001 TIN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 10 I_10 1010 TIN1 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz 11 I_11 1011 TIN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default (Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz 12/1 (Note (iii)) I_12 1100 TIN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 13 I_13 1101 TIN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 14 I_14 1110 TIN2 TTL/CMOS Up to 100 MHz (see Note (i)) Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz 15 Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH is selected using the SONSDHB pin. When the SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected. (ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz. (iii) Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin. DivN Examples the frequency to 6.48 MHz. (XX = "leaky bucket" ID for this input). To lock to 2.000 MHz. 1. The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the frequency to E1/DS1. (XX = "leaky bucket" ID for this input). 2. The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1). 3. The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. 4. The DivN register is set to F9 Hex (249 decimal). To lock to 10.000 MHz. 1. The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and Revision 2.02/June 2006 (c) Semtech Corp. 2. The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. 3. The DivN register is set to 4E1 Hex (1249 decimal). PECL and LVDS ports support the spot clock frequencies listed plus 155.52 MHz and 311.04 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other input low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled high and the other low. An AMI port supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703. Departures from the Page 11 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL nominal pattern are detected within the ACS8510 Rev2.1, and may cause reference-switching if too frequent. See "DC Characteristics: AMI Input/Output Port" on page 53 for more details. If the AMI port is unused, the pins (I1 and I2) should be tied to GND and the VAMI+ supply pin (pin 26) disconnected. Input Wander and Jitter Tolerance The ACS8510 Rev2.1 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI DS1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for each input port in Table 7. Minimum jitter tolerance masks are specified in Figures 3 and 4, and Tables 8 and 9, respectively. The ACS8510 Rev2.1 will tolerate wander and jitter components greater than those shown in Figure 3 and Figure 4, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). The "8klocking" mode should be engaged for high jitter tolerance according to these masks. All reference DATASHEET clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. The registers sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This is a 19-bit signed number with one LSB representing 0.0003 ppm (range of 80 ppm). Reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. The ACS8510 Rev2.1 performs automatic frequency monitoring with an acceptable input frequency offset range of 16.6 ppm. The ACS8510 Rev2.1 DPLL has a programmable frequency limit of 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range.. Table 7 Input Reference Source Jitter Tolerance Jitter Tolerance Frequency Monitor Acceptance Range G.703 G.783 Frequency Acceptance Range (Pull-in) Frequency Acceptance Range (Hold-in) Frequency Acceptance Range (Pull-out) 4.6 ppm (see Note (i)) 4.6 ppm (see Note (i)) 4.6 ppm (see Note (i)) 9.2 ppm (see Note (ii)) 9.2 ppm (see Note (ii)) 9.2 ppm (see Note (ii)) 16.6 ppm G.823 GR-1244-CORE Notes: (i) The frequency acceptance and generation range will be 4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of 4.6 ppm. (ii) The fundamental acceptance range and generation range is 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Revision 2.02/June 2006 (c) Semtech Corp. Page 12 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 3 Minimum Input Jitter Tolerance (OC-3/STM-1) A0 A1 A2 A3 A4 Jitter and Wander Frequency (log scale) f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 F8530_003MINIPJITTOLOC3STM1_02 Note...For inputs supporting G.783[9] compliant sources.) Table 8 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1) STM level Peak to peak amplitude (unit Interval) A0 STM-1 2800 A1 A2 A3 A4 311 39 1.5 0.15 Frequency (Hz) F0 F1 12 u 178 u 1.6 m Frame Sync and MultiFrame Sync Clocks (Part of TOUT0) F3 15.6 m F4 0.125 F5 F6 19.3 500 F7 F8 F9 6.5 k 65 k 1.3m Low-speed Output Clock (TOUT4) Frame Sync (8 kHz) and MultiFrame Sync (2 kHz) clocks are provided on outputs TO10 (FrSync) and TO11 (MFrSync). The FrSync and MFrSync clocks have a 50:50 mark space ratio. These are driven from the TOUT0 clock. They are synchronized with their counterparts in a second ACS8510 Rev2.1 device (if used), using the technique described later. Output Clock Ports The device supports a set of main output clocks, TOUT0 and TOUT4, and a pair of secondary output clocks, "FrameSync" and "Multi-Frame-Sync". The two main output clocks, TOUT0 and TOUT4, are independent of each other and are individually selectable. The two secondary output clocks, Frame-Sync and Multi-Frame-Sync, are derived from TOUT0. The frequencies of the output clocks are selectable from a range of pre-defined spot frequencies and a variety of output technologies are supported, as defined in Table 10. Revision 2.02/June 2006 (c) Semtech Corp. F2 The TOUT4 clock is supplied on two output ports, TO8 and TO9. The former port will provide an AMI signal carrying a composite clock of 64 kHz and 8 kHz, according to ITU Recommendation G.703. The latter port will provide a TTL/CMOS signal at either 1.544 MHz or 2.048 MHz, depending on the setting of the SONSDHB pin. High-speed Output Clock (Part of TOUT0) The TOUT0 port has multiple outputs. Outputs TO1and TO2 are TTL/CMOS output with a choice of 11 different frequencies up to 51.84 MHz. Outputs TO3 to TO5 are all TTL/CMOS outputs with fixed frequencies of 19.44 MHz, 38.88 MHz and 77.76 MHz respectively. Output TO6 is differential and can support clocks up to 155.52 MHz. Output TO7 is also differential and can support clocks up to 155.52 MHz. Each output is individually configured to operate at the frequencies shown in Table 10 (configuration must be consistent between ACS8510 Rev2.1 devices for protection-switching to be effective output clocks will be phase-aligned between devices). Using the cnfg_differential_outputs register, outputs TO6 and TO7 can be made to be LVDS or PECL compatible. Page 13 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 4 Minimum Input Jitter Tolerance (DS1/E1) Peak-to-peak Jitter and Wander Amplitude (log scale) A1 A2 Jitter and Wander Frequency (log scale) f1 f2 f3 F8530D_004MINIPJITTOLDS1E1_02 f4 Table 9 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1) Type Spec. Amplitude (UIp-p) A1 Frequency (Hz) A2 F1 F2 F3 F4 DS1 GR-1244-CORE[19] 5 0.1 10 500 8k 40 k E1 ITU G.823[13] 1.5 0.2 20 2.4 k 18 k 100k Low Jitter Multiple E1/DS1 Outputs This feature added to Rev2.1 is activated using the cnfg_control1 register. This sends a frequency of twice the Dig2 rate (see reg addr 39h, bits 7:6) to the APLL instead of the normal 77.76 MHz. For this feature to be used, the Dig2 rate must only be set to 12352 kHz/16384 kHz using the cnfg_T0_output_frequencies register. The normal OC-3 rate outputs are then replaced with E1/DS1 multiple rates. The E1(SONET)/DS1(SDH) selection is made in the same way as for Dig2 using the cnfg_T0_output_enable register. Table 11 shows the relationship between primary output frequencies and the corresponding output in E1/DS1 mode, and which output they are available from. Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: 1. The magnitude of wander and jitter on the selected input reference clock (in Locked mode) Revision 2.02/June 2006 (c) Semtech Corp. 2. The internal wander and jitter transfer characteristic (in Locked mode) 3. The jitter on the local oscillator clock 4. The wander on the local oscillator clock (in Holdover mode). Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. Wander and jitter attenuation is performed using a digital phase locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. Since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. Strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. But, since any buffer store potentially Page 14 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 10 Output Reference Source Selection Table Port Name Output Port Technology Frequencies Supported T01 TTL/CMOS 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 6.48 MHz (default), 12.352 MHz/16.384 MHz, 19.44 MHz, 25.92 MHz T02 TTL/CMOS 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 12.352 MHz/16.384 MHz, 25.92 MHz, 38.88 MHz (default), 51.84 MHz T03 TTL/CMOS 19.44 MHz - fixed T04 TTL/CMOS 38.88 MHz - fixed T05 TTL/CMOS 77.76 MHz - fixed T06 LVDS/PECL (LVDS default) 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 12.352 MHz/16.384 MHz, 19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz T07 PECL/LVDS (PECL default) 19.44 MHz (default), 51.84 MHz, 77.76 MHz, 155.52 MHz T08 AMI 64/8 kHz (composite clock, 64 kHz + 8 kHz) T09 TTL/CMOS 1.544 MHz/2.048 MHz T010 TTL/CMOS FrSync, 8 kHz - with a 50:50 MSR T011 TTL/CMOS MFrSync, 2 kHz - with a 50:50 MSR Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default. Table 11 Multiple E1/DS1 Outputs in Relation to Standard Outputs Mode Freq to APLL APLL Multiplier Defaul 77.76 t 4 APLL Freq 311.04 clk_ filt 311.04 clk_ filt/2 clk_ filt/4 155.52 77.76 n value clk_ filt/6 51.84 16 clk_ filt/8 38.88 clk_ filt/12 25.92 8 clk_ filt/16 19.44 clk_ filt/48 6.48 DPLL Freq 77.76 4 n x E1 32.768 4 131.072 131.072 65.536 32.768 21.84533 16.384 10.92267 8.192 2.730667 77.76 n x T1 98.816 16.46933 12.352 8.234667 6.176 2.058667 77.76 24.704 4 98.816 49.408 24.704 T01 T02 T03 Frequencies Available by Output T04 T05 T06 T06 T07 Revision 2.02/June 2006 (c) Semtech Corp. Page 15 T06 T07 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8510 Rev2.1 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 5. Wander on the local oscillator clock will not have significant effect on the output clock whilst in Locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable DATASHEET component for the local oscillator, as specified in the Section "Local Oscillator Clock" on page 8. Phase Variation There will be a phase shift across the ACS8510 Rev2.1 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterized using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevant specifications, differ in acceptable limits in each one. Typical measurements for the ACS8510 Rev2.1 are shown in Figures 6 and 7, for Locked mode operation. Figure 8 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances pertaining: Figure 5 Sample of Wander and Jitter Measured Transfer Characteristics F8530D_005WANJITTXFR_04bitmap.bmp Revision 2.02/June 2006 (c) Semtech Corp. Page 16 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET 1. ETSI 300 462-5, Section 9.1, requires that the short term phase error during switchover (i.e., Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. slips (of 125 s each) occur during the first day of Holdover. This requires a frequency accuracy better than: 2. ETSI 300 462-5, Section 9.2, requires that the long term phase error in the Holdover mode should not exceed Temperature variation is not restricted, except to within the normal bounds of 0 to 50 C. ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm 4. Telcordia GR.1244.CORE, Section 5.2., Table 4, shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. {(a1+a2)S+0.5bS2+c} where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16 x 10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). 5. ITU G.822, Section 2.6, requires that the slip rate during category (b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour: 3. ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 ((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm Figure 6 Maximum Time Interval Error of Tout0 Output Port Figure 7 Time Deviation of Tout0 Output Port Revision 2.02/June 2006 (c) Semtech Corp. Page 17 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 8 Phase Error Accumulation of T0 PLL Output Port in Holdover Mode 10000000 Phase Error (ns) 1000000 Permitted Phase Error Limit 100000 10000 1000 100 Typical measurement, 25C constant temperature 10000 1000 Phase Build-Out Phase Build-Out (PBO) is the function to minimize phase transients on the output SEC clock during input reference switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. During this transition, the Lost_Phase mode is entered. The typical phase disturbance on clock reference source switching will be less than 12 ns on the ACS8510 Rev2.1. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the G.813 spec. The actual value is dependent on the frequency being locked to. Revision 2.02/June 2006 (c) Semtech Corp. 100000 Observation interval (s) ITU-T G.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. On the ACS8510 Rev2.1, PBO can be enabled, disabled or frozen using the P interface. By default, it is enabled. When PBO is enabled, it can also be frozen, which will disable the PBO operation on the next input reference switch, but will remain with the current offset. If PBO is disabled while the device is in the Locked mode, there will be a phase jump on the output SEC clocks as the DPLL locks back to 0 degree phase error. Page 18 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Microprocessor Interface FINAL value is stored sequentially, with ROM address 0 corresponding to register address 0 and so on. The ACS8510 Rev2.1 incorporates a microprocessor interface, which can be configured for the following modes via the bus interface mode control pins UPSEL(2:0) as defined in Table 12. The value in the chip_id location (address 00 & 01) is checked to see if it matches the ID number of the ACS8510 Rev2.1 (value 213E). Upon a successful number match, the remaining data from the ROM is used to set the internal register values. Only 64 locations in the ROM are required. Table 12 Microprocessor Interface Mode Selection UPSEL(2:0) Mode Description 111 (7) OFF Interface disabled 110 (6) OFF Interface disabled 101 (5) SERIAL Serial uP bus interface 100 (4) MOTOROLA Motorola interface 011 (3) INTEL Intel compatible bus interface 010 (2) MULTIPLEXED Multiplexed bus interface 001 (1) EPROM EPROM read mode 000 (0) OFF Interface disabled DATASHEET Register Set All registers are 8-bits wide, organized with the mostsignificant bit positioned in the left-most bit, with bit significance decreasing towards the right most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers; their organization is shown in the register map, Table 13. Configuration Registers Motorola Mode Parallel data + address: this mode is suitable for use with Motorola's 68x0 type bus. Intel Mode Parallel data + address: this mode is suitable for use with Intel's 80x86 type bus. Multiplexed Mode Data/address: this mode is suitable for use with microprocessors which share bus signals between address and data (e.g., Intel's 80x86 family). Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pinsettable. All configuration registers can be read out over the microprocessor port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. Serial Mode Register Access This mode is suitable for use with microprocessor which use a serial interface. Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_ID and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a "1" into each bit of the field (writing a "0" value into a bit will not affect the value of the bit). A description of each register is given in the Register Map, and Register Map Description. EPROM Mode This mode is suitable for simple standalone applications where it is required to change the default loading of the register values to suit different applications. This can be done by loading values from an external ROM. The data is read from the ROM automatically after powerup when the UPSEL(2:0) pins are set to "001". Each register Revision 2.02/June 2006 (c) Semtech Corp. Page 19 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Interrupt Enable and Clear FINAL Interrupt requests are flagged on pin INTREQ (active High). Bits in the interrupt status register are set (high) by the following conditions: 1. Any reference source becoming valid or going invalid 2. A change in the operating state (e.g. Locked, Holdover etc.) 3. A brief loss of the currently selected reference source 4. An AMI input error DATASHEET failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the "main reference failed" interrupt (addr 06, bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to bit 6 of register 48Hex. Register Map All interrupt sources are maskable via the mask register, each one being enabled by writing a "1" to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. The fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source Shaded areas in the map are "don't care" and writing either 0 or 1 will not affect any function of the device. Bits labelled Set to 0 or Set to 1 must be set as stated during initialization of the device, either following power up, or after a power on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. Some registers do not appear in this list. These are either not used, or have test functionality. Do not write to any undefined registers as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. Table 13 Register Map Addr (Hex) 00 01 Register Name 7 (msb) 6 5 4 chip_id (read only) 02 chip_revision (read only) 03 cnfg_control1 (read/write) 04 cnfg_control2 (read/write) 05 sts_interrupts (read/write) 06 Data Bit 3 2 1 0 (lsb) Device part number (7:0) Device part number (15:8) Chip revision number (7:0) Multiple E1/T1 O/P Analog div sync Set to 0 Phase loss flag limit 8k Edge Polarity Set to 0 Set to 0 Set to 0 Set to 1 Set to 0 <I_8> valid <I_7> valid <I_6> valid <I_5> valid <I_4> valid <I_3> valid <I_2> valid <I_1> valid change change change change change change change change Operating mode Revision 2.02/June 2006 (c) Semtech Corp. Main ref. failed <I_14> valid change Page 20 <I_13> valid change <I_12> valid change <I_11> valid change <I_10> valid change <I_19> valid change www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 13 Register Map Addr (Hex) Register Name 7 (msb) 08 sts_T4_inputs (read/write) 09 sts_operating_mode (read only) 0A sts_priority_table (read only) 0B 0C 0D Data Bit 6 5 4 3 T4 ref failed Ami2 Violation 0F 10 Ami2 L.O.S. 1 0 (lsb) Ami1 Violation Ami1 L.O.S. Operating mode (2:0) Highest priority valid source Currently selected reference source 3rd highest priority valid source 2nd highest priority valid source sts_curr_inc_offset (read only) Current increment offset (7:0) Current increment offset (15:8) 07 0E 2 Current increment offset (18:16) sts_sources_valid (read only) <I_8> <I_6> <I_5> <I_4> <I_3> <I_2> <I_1> <I_14> <I_13> <I_12> <I_11> <I_10> <I_19> status <I_2> status <I_1> status <I_4> status <I_3> 12 status <I_6> status <I_5> 13 status <I_8> status <I_7> 14 status <I_10> status <I_9> 15 status <I_12> status <I_11> 16 status <I_14> status <I_13> programmed_priority <I_2> programmed_priority <I_1> programmed_priority <I_4> programmed_priority <I_3> 1A programmed_priority <I_6> programmed_priority <I_5> 1B programmed_priority <I_8> programmed_priority <I_7> 1C programmed_priority <I_10> programmed_priority <I_9> 1D programmed_priority <I_12> programmed_priority <I_11> 1E programmed_priority <I_14> programmed_priority <I_13> 11 18 19 sts_reference_sources (read/write) <I_7> cnfg_ref_selection_ priority (read/write) Revision 2.02/June 2006 (c) Semtech Corp. Page 21 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 13 Register Map Addr (Hex) 20 Register Name Data Bit 7 (msb) 5 4 3 2 1 0 (lsb) divn lock8k bucket_id <I_1>(1:0) reference_source_frequency <I_1>(3:0) divn lock8k bucket_id <I_2>(1:0) reference_source_frequency <I_2>(3:0) 22 divn lock8k bucket_id <I_3>(1:0) reference_source_frequency <I_3>(3:0) 23 divn lock8k bucket_id <I_4>(1:0) reference_source_frequency <I_4>(3:0) 24 divn lock8k bucket_id <I_5>(1:0) reference_source_frequency <I_5>(3:0) 25 divn lock8k bucket_id <I_6>(1:0) reference_source_frequency <I_6>(3:0) 26 divn lock8k bucket_id <I_7>(1:0) reference_source_frequency <I_7>(3:0) 27 divn lock8k bucket_id <I_8>(1:0) reference_source_frequency <I_8>(3:0) 28 divn lock8k bucket_id <I_9>(1:0) reference_source_frequency <I_9>(3:0) 29 divn lock8k bucket_id <I_10>(1:0) reference_source_frequency <I_10>(3:0) 2A divn lock8k bucket_id <I_11>(1:0) reference_source_frequency <I_11>(3:0) 2B divn lock8k bucket_id <I_12>(1:0) reference_source_frequency <I_12>(3:0) 2C divn lock8k bucket_id <I_13>(1:0) reference_source_frequency <I_13>(3:0) 2D divn lock8k bucket_id <I_14>(1:0) reference_source_frequency <I_14>(3:0) 21 30 31 cnfg_ref_source_ frequency (read/write) 6 cnfg_sts_remote_ sources_ valid (read/write) 32 cnfg_operating_mode (read/write) 33 cnfg_ref_selection (read/write) 34 cnfg_mode (read/write) 35 cnfg_T4 (read/write) 36 cnfg_differential_inputs (read/write) 37 cnfg_uPsel_pins (read only) 38 cnfg_T0_output_enable (read/write) 39 cnfg_T0_output_ frequencies (read/write) Remote status, channels <8:1> Remote status, channels <14:9> Forced operating mode force_select_reference_source Auto external 2K enable Phase alarm timeout enable Clock edge Holdover Offset enable Squelch Select T0/T1 External 2K SONET/ Sync SDH enable I/P Master/ Slave Reversion mode Force T1 input source selection (only valid for inputs I_5 to I_10) <I_6> PECL <I_5> PECL Microprocessor type 311.04 1=SONET MHz on T06 0=SDH for Dig2 Revision 2.02/June 2006 (c) Semtech Corp. Digital2 1=SONET 0=SDH for Dig1 T01 Digital1 Page 22 T02 T03 19.44 MHz T02 T04 T05 38.88 MHz 77.76 MHz T01 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 13 Register Map Addr (Hex) Register Name Data Bit 7 (msb) 6 3A cnfg_differential_ outputs (read/write) T07 Frequency selection 3B cnfg_bandwidth (read/write) Auto b/w switch Acq/lock 3C cnfg_nominal_frequency (read/write) 3D 3E 3F 42 43 4 T06 Frequency selection T07 PECL enable Set to 0 0 (lsb) T06 LVDS enable T06 PECL enable Normal/locked bandwidth Nominal frequency (15:8) Holdover offset (7:0) Holdover offset (15:8) Holdover offset (18:16) cnfg_freq_limit (read/write) cnfg_interrupt_mask (read/write) 1 Nominal frequency (7:0) DPLL Frequency offset limit (7:0) DPLL Frequency offset limit (9:8) <I_8> valid <I_7> valid <I_6> valid <I_5> valid <I_4> valid <I_3> valid <I_2> valid <I_1> valid change change change change change change change change Operating mode Main ref. failed <I_14> valid change 45 47 2 Auto Holdover Averagin 44 46 3 T07 LVDS enable Acquisition bandwidth cnfg_holdover_offset (read/write) 40 41 5 cnfg_freq_divn (read/write) <I_13> valid change <I_12> valid change <I_11> valid change <I_10> valid change <I_19> valid change T4 ref Ami2 Violation Ami2 L.O.S Ami1 Violation Ami1 L.O.S Divide-input-by-n ratio (7:0) Divide-input-by-n ratio (13:8) 48 cnfg_monitors (read/write) 50 cnfg_activ_upper_ threshold0 (read/write) Configuration 0: Activity alarm set threshold (7:0) 51 cnfg_activ_lower_ threshold0 (read/write) Configuration 0: Activity alarm reset threshold (7:0) 52 cnfg_bucket_size0 (read/write) Configuration 0: Activity alarm bucket size (7:0) 53 cnfg_decay_rate0 (read/write) Revision 2.02/June 2006 (c) Semtech Corp. Flag ref lost Ultra-fast on TDO switching External source switch enable Freeze phase buildout Phase buildout enable Frequency monitors configuration (1:0) Cfg 0:decay_rate (1:0) Page 23 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 13 Register Map Addr (Hex) Register Name Data Bit 7 (msb) 6 5 4 3 2 54 cnfg_activ_upper_ threshold1 (read/write) Configuration 1: Activity alarm set threshold (7:0) 55 cnfg_activ_lower_ threshold1 (read/write) Configuration 1: Activity alarm reset threshold (7:0) 56 cnfg_bucket_size1 (read/write) Configuration 1: Activity alarm bucket size (7:0) 57 cnfg_decay_rate1 (read/write) 58 cnfg_activ_upper_ threshold2 (read/write) Configuration 2: Activity alarm set threshold (7:0) 59 cnfg_activ_lower_ threshold2 (read/write) Configuration 2: Activity alarm reset threshold (7:0) 5A cnfg_bucket_size2 (read/write) Configuration 2: Activity alarm bucket size (7:0) 5B cnfg_decay_rate2 (read/write) 5C cnfg_activ_upper_ threshold3 (read/write) Configuration 3: Activity alarm set threshold (7:0) 5D cnfg_activ_lower_ threshold3 (read/write) Configuration 3: Activity alarm reset threshold (7:0) 5E cnfg_bucket_size3 (read/write) Configuration 3: Activity alarm bucket size (7:0) 5F cnfg_decay_rate3 (read/write) 7F cnfg_uPsel (read/write) Revision 2.02/June 2006 (c) Semtech Corp. 1 0 (lsb) Cfg 1:decay_rate (1:0) Cfg 2:decay_rate (1:0) Cfg 3:decay_rate (1:0) Micro-processor type Page 24 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Register Map Description FINAL DATASHEET Table 14 Register Description Addr. (Hex) Register Name chip_id Description Default Value (Bin) This register contains the chip ID = 8510 (decimal) 00 Bits (7:0) Chip ID bits (7:0 00111110 01 Bits (7:0) Chip ID bits (15:8) 00100001 This read only register contains the chip revision number This revision = 1 Last revision (engineering samples) = 0 00000001 02 03 chip_revision cnfg_control1 Bits (7:6) Unused Bit 5 =1 32/24 MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76 MHz. Thus the normal OC-3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits (Reg. 39h Bits (7:6)) must be set to 11 for this mode. =0 77.76MHz to APLL Bit 4 =1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section such that their phases align. This is necessary in order to have phase alignment between inputs and output clocks at OC-3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be necessary to avoid the dividers getting out of synchronization when quick changes in frequency occur such as a force into FreeRun. =0 The dividers may get out of phase following step changes in frequency, but in this mode the correct number of high frequency edges is guaranteed within any synchronization period. The output will frequency lock (default). The device will always remain in synchronization 2 seconds from a reset, before the default setting applies. Bits 3 XX000000 Test control - leave unchanged, or set to 0 Bit 2 =1 When in 8k locking mode the system will lock to the rising input clock edge. =0 When in 8k locking mode the system will lock to the falling input clock edge. Bits (1:0) Test controls - leave unchanged, or set to 00 04 cnfg_control2 Bits (7:6) Unused Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds to approximately 140. A lower value sets a corresponding lower phase limit. The flag limit determines the value at which the DPLL indicates phase lost as a result of input jitter, a phase jump, or a frequency jump on the input XX100010 Bits (2:0) Test controls - leave unchanged, or set to 010 05 06 sts_interrupts Bits (7:0) <I_8> to <I_1> 00000000 Bits (7:0) Operating mode, main ref failed, <I_14> to <I_9> 00000000 Revision 2.02/June 2006 (c) Semtech Corp. Page 25 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 08 Register Name sts_T4_inputs Description Default Value (Bin) This register holds the status flags of the AMI inputs and the TOUT4 reference. The alarms once set will hold their state until reset. Each bit may be cleared individually by writing a "1" to that bit, thus resetting the interrupt. Writing "0"s will have no effect. These bits can also generate interrupts. Bits (7:5) Unused. Bit 4 =1 =0 Bit 3 =1 =0 Bit 2 =1 =0 Bit 1 =1 =0 Bit 0 =1 =0 09 sts_operating_mode T4 reference failed - no valid TIN1 input (<I_10>:<I_5>), T4 DPLL cannot lock to source (default) T4 reference good - valid TIN1 input available. XXX10000 Ami2 Violation detected Ami2 clear (default) Ami2 Loss of signal Ami2 clear (default) Ami1 Violation detected Ami1 clear (default) Ami1 Loss of signal Ami1 clear (default) This read-only register holds the current operating state of the main state machine. Figure 11 shows how the values of the "operating state" variable match with the individual states. Bits (7:3) Unused. Bits (2:0) 001 010 100 110 101 111 Revision 2.02/June 2006 (c) Semtech Corp. State Free-Run (default) Holdover Locked Pre-locked Pre-locked2 Phase lost XXXXX001 Page 26 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) Register Name sts_priority_table Description Default Value (Bin) This is a 16-bit read-only register. Bits (15:12) Third highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the secondhighest-priority valid source. Bits (11:8) Second highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the highestpriority valid source. Bits (7:4) Highest priority valid source: this is the channel number of the input reference source which is valid and has the highest priority - it may not be the same as the currently selected reference source (due to failure history or changes in programmed priority). Bits (3:0) Currently selected reference source: this is the channel number of the input reference source which is currently input to DPLL. Note that these registers are updated by the state machine in response to the contents of the cnfg_ref_selection_priority register and the ongoing status of individual channels; channel number "0000", appearing in any of these registers, indicates that no channel is available for that priority. 0A Bits (7:4) Highest priority valid source (sts_priority_table bits (7:4)) Bits (3:0) Currently selected reference source (sts_priority_table bits (3:0)) 0000000 0B Bits (7:4) 3rd-highest priority valid source (sts_priority_table bits (15:12)) Bits (3:0) 2nd-highest priority valid source (sts_priority_table bits (11:8)) 0000000 sts_curr_inc_offset This read-only register contains a signed-integer value representing the 19 significant bits of the current increment offset of the digital PLL. The register may be read periodically to build up a historical database for later use during holdover periods (this would only be necessary if an external oscillator which did not meet the stability criteria described in Local Oscillator Clock section is used). The register will read 00000000 immediately after reset. 0C Bits (7:0) sts_curr_inc_offset bits (7:0) 00000000 0D Bits (7:0) sts_curr_inc_offset bits (15:8) 00000000 07 Bits (7:3) Unused Bits (2:0) sts_curr_inc_offset bits (18:16) XXXXX000 sts_sources_valid This register contains a bit to show validity for every reference source. =1 Valid source =0 Invalid source (default) 0E Bits (7:0) <I_8> to <I_1> 00000000 0F Bits (7:6) Unused Bits (5:0) <I_14> to <I_9> XX000000 Revision 2.02/June 2006 (c) Semtech Corp. Page 27 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) Register Name sts_reference_sources Description Default Value (Bin) This is a 7-byte register which holds the status of each of the 14 input reference sources. The status of each reference source is shown in a 4-bit field. Each bit is active high.To aid status checking, a copy of each status bit 3 is provided in the sts_sources_valid register. The status is reported as follows: (Each bit may be cleared individually) Status bit 3 = Source valid (no alarms) (bit 3 is combination of bits (2:0)) (default 0) Status bit 2 = out-of-band alarm (default 1) Status bit 1 = no activity alarm (default 1) Status bit 0 = phase lock alarm (default 0) 10 Bits (7:4) Status of input reference source <I_2> Bits (3:0) Status of input reference source <I_1> 01100110 11 Bits (7:4) Status of input reference source <I_4> Bits (3:0) Status of input reference source <I_3> 01100110 12 Bits (7:4) Status of input reference source <I_6> Bits (3:0) Status of input reference source <I_5> 01100110 13 Bits (7:4) Status of input reference source <I_8> Bits (3:0) Status of input reference source <I_7> 01100110 14 Bits (7:4) Status of input reference source <I_10> Bits (3:0) Status of input reference source <I_9> 01100110 15 Bits (7:4) Status of input reference source <I_12> Bits (3:0) Status of input reference source <I_11> 01100110 16 Bits (7:4) Status of input reference source <I_14> Bits (3:0) Status of input reference source <I_13> 01100110 cnfg_ref_selection_ priority This register holds the priority of each of the 14 input reference sources. The priority values are all relative to each other, with lower-valued numbers taking higher priorities. Only the values "1" to "15" (dec) are valid - "0" disables the reference source. Each reference source should be given a unique number, however two sources given the same priority number will be assigned on a first in first out basis. It is recommended to reserve the priority value "1" as this is used when forcing reference selection via the cnfg_ref_selection register. If the user does not intend to use the cnfg_ref_selection register then the priority value "1" need not be reserved. 18 Bits (7:4) Programmed priority of input reference source <I_2> 00110010 Bits (3:0) Programmed priority of input reference source <I_1> 19 Bits (7:4) Programmed priority of input reference source <I_4> 01010100 Bits (3:0) Programmed priority of input reference source <I_3> 1A Bits (7:4) Programmed priority of input reference source <I_6> 01110110 Bits (3:0) Programmed priority of input reference source <I_5> 1B Bits (7:4) Programmed priority of input reference source <I_8> 10011000 Bits (3:0) Programmed priority of input reference source <I_7> Revision 2.02/June 2006 (c) Semtech Corp. Page 28 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 1C Register Name cnfg_ref_selection_ priority (continued) 1D Description Bits (7:4)Programmed priority of input reference source <I_10> 10111010 Bits (3:0)Programmed priority of input reference source <I_9> Bits (7:4)Programmed priority of input reference source <I_12> Bits (3:0)Programmed priority of input reference source <I_11> 1E Default Value (Bin) 11010001 (MSTSLVB=0) 11011100 (MSTSLVB=1) Bits (7:4)Programmed priority of input reference source <I_14> 11111110 Bits (3:0)Programmed priority of input reference source <I_13> cnfg_ref_source_ frequency This register is used to set up each of the 14 input reference sources. Bits (7:6) of each byte defines the operation undertaken on the input frequency, in accordance with the following key: 00 01 10 11 The input frequency is fed directly into the DPLL. (default). The input frequency is internally divided down to 8 kHz, before being fed into the DPLL. (For high jitter tolerance). Unsupported configuration - do not use. Uses the division coefficient stored in registers 46 and 47 (cnfg_freq_divn) to divide the input by this value prior to being fed into the DPLL. The frequency monitors must be disabled. The divided down frequency should equal 8 kHz. The frequency (3:0) should be set to the nearest spot frequency just below the actual input frequency. The DivN feature works for input frequencies between 1.544 MHz and 100 MHz. Bits (5:4) define which leaky bucket group (0-3) is used, as defined in registers 50 to 5F. (default 00). Bits (3:0) defines the frequency of the reference source in accordance with the following: 0000 8 kHz (fixed <I_1>, <I_2>, default <I_3>, <I_4>) 0001 1.544 MHz (SONET)/2.048 MHz (SDH) (as defined by register 34, bit 2) (default <I_12>, <I_13>, <I_14>) 0010 6.48 MHz (default <I_11> when MSTSLVB = 1) 0011 19.44 MHz (default <I_11> when MSTSLVB=0, and <I_5>, <I_6>, <I_7> <I_8>, <I_9>, <I_10>) 0100 25.92 MHz 0101 38.88 MHz 0110 51.84 MHz 0111 77.76 MHz 1000 155.52 MHz 1001 2 kHz 1010 4 kHz 20 Frequency of reference source <I_1> - fixed at 00000000 for 8 kHz only 00000000 21 Frequency of reference source <I_2> - fixed at 00000000 for 8 kHz only 00000000 22 Frequency of reference source <I_3> 00000000 23 Frequency of reference source <I_4> 00000000 Revision 2.02/June 2006 (c) Semtech Corp. Page 29 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 24 Register Name Default Value (Bin) Frequency of reference source <I_5> 00000011 Frequency of reference source <I_6> 00000011 26 Frequency of reference source <I_7> 00000011 27 Frequency of reference source <I_8> 00000011 28 Frequency of reference source <I_9> 00000011 29 Frequency of reference source <I_10> 00000011 2A Frequency of reference source <I_11> 00000010 (MSTSLVB=0) 00000011 (MSTSLVB=1) 2B Frequency of reference source <I_12> 00000001 2C Frequency of reference source <I_13> 00000001 2D Frequency of reference source <I_14> 00000001 25 cnfg_ref_source_ frequency (continued) Description cnfg_sts_remote_ sources_ valid This register holds the status of the reference sources supplied to the other device in a master/slave configuration. It is a copy of the other device's sts_sources_valid register. The register is part of the protection mechanism. 30 Bits (7:0) Reference sources <I_8>:<I_1> 11111111 31 Bits (7:6) Unused Bits (5:0) Reference sources <I_14>:<I_9> XX111111 32 cnfg_operating_mode This register is used to force the device into a desired operating state, represented by the binary values shown in Figure 11. Value 0 (hex) allows the control state machine to operate automatically. XXXXX000 Bits (7:3)Unused Bits (2:0)Desired operating state (as per Figure 11) 33 cnfg_ref_selection This register is used to force the device to select a particular input reference source, irrespective of its priority. Writing to this register temporarily raises the selected input to priority "1". Provided no other input is already programmed with priority "1", and revertive mode is on, this source will be selected.. XXXx1111 Bits (7:4) Unused. Bits (3:0) Desired reference source (0000 and 1111 disables the force selection, and allows automatic selection of all sources, default is 1111) Revision 2.02/June 2006 (c) Semtech Corp. Page 30 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 34 Register Name cnfg_mode Description Default Value (Bin) This register contains several individual configuration fields, as detailed below: Bit 7 =1 Auto 2 kHz Sync enable: External 2 kHz Sync will be enabled only when the source is locked to 6.48 MHz. Otherwise it will be disabled (default) =0 Auto 2 kHz Sync disable: The user controls this function using bit 3 of this register, as described below. Bit 6 =1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds (default). =0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset by software. Bit 5 =1 Rising Clock Edge selected: The device will reference to the rising edge of the external 12.8 MHz crystal oscillator signal =0 Falling edge Edge selected: The device will reference to the falling edge of the external 12.8 MHz crystal oscillator signal (default). Bit 4 =1 Holdover offset enable: The device will adopt the Holdover offset value stored in the cnfg_holdover_offset register, in order to set the frequency in Holdover =0 Holdover offset disable: The device will ignore the value and Holdover will freeze the frequency of the DPLL on entering Holdover mode (default). Bit 3 = 1 External 2 kHz Sync Enable: The device will align the phase of its internally generated Frame Sync signal (8 kHz) and MultiFrame Sync signal (2 kHz) with that of the signal supplied to the Sync2K pin. The device should be locked to a 6.48 MHz output from another ACS8510 Rev2.1. = 0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin. Bit 2 = 1 SONET Mode: The device expects the input frequency of any input channel given the value '0001' in the cnfg_ref_source_frequency register to be 1544 kHz = 0 SDH Mode: The device expects the input frequency of any input channel given the value "0001" in the cnfg_ref_source_frequency register to be 2048 kHz. At start up or reset the bit value will be defaulted to the setting of pin SONSDHB. This setting can subsequently be altered by changing this bit value. 11001000 (MSTSLVB=0) (SONSDHB=0) 11001100 (MSTSLVB=0) (SONSDHB=1) 11000010 (MSTSLVB=1) (SONSDHB=0) 11000110 (MSTSLVB=1) (SONSDHB=1) Bit 1 = 1 Master Mode: The device will adopt the master mode and make the active decisions of which source to select, etc. This bit is writeable, but its default value is determined by the pin, MSTSLVB. = 0 Slave Mode: The device will adopt the slave mode and will follow the master device. At start up or reset the bit value will be defaulted to the setting of pin MSTSLVB. This setting can subsequently be altered by changing this bit value. Bit 0 = 1 Revertive Mode: The device will switch to the highest priority source available shown in the sts_priority_table register, bits (7:4) = 0 Non Revertive Mode: The device will retain the presently selected source (default) Revision 2.02/June 2006 (c) Semtech Corp. Page 31 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 35 Register Name cnfg_T4 Description Default Value (Bin) This controls DPLL _T4 (output on TO8/TO9) and input source selection: Bits (7:6) Unused Bit 5 =1 =0 DPLL_T4 is turned off (squelched) DPLL_T4 is on (default) Bit 4 =1 =0 Selects which DPLL (T4 or T0) source feeds outputs TO8/TO9: DPLL_T0 output is fed to outputs TO8 and TO9 DPLL_T4 output is fed to outputs TO8 and TO9 XX000000 Bits (3:0) Input source selection. The device will switch to the source shown in this field for the generation of the TOUT4 signal. If '0' it will select the highest priority active TIN1. 36 cnfg_differential_inputs This register contains two individual configuration fields, as follows: Bits (7:2) Unused 37 cnfg_uPsel_pins Bit 1 =1 =0 Input <I_6> is PECL-compatible (Default) Input <I_6> is LVDS-compatible Bit 0 =1 =0 Input <I_5> is PECL-compatible Input <I_5> is LVDS-compatible (Default) This read only register returns a value indicating the microprocessor type selected at power up or reset. This is set by the configuration of the UPSEL pins (pins 58 - 60). If the UPSEL pin configuration is changed while the device is operating no effect will take place, but this register will reflect that change, so indicating the configuration that will be implemented at the next power up or reset. The microprocessor type can be changed with the device operational, though register 7F. Bits (7:3) Unused. Bit (2:0) 000 001 010 011 100 101 110 111 Revision 2.02/June 2006 (c) Semtech Corp. Microprocessor type OFF (interface disabled) EPROM MULTIPLEXED INTEL MOTOROLA SERIAL OFF (interface disabled) OFF (interface disabled) Page 32 XXXXXX10 Bits(7:3)= XXXXX Bits(2:0)= UPSEL pin configuration www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 38 Register Name cnfg_T0_output_enable Description Default Value (Bin) This register contains several individual configuration fields, as follows: Bit 7 =1 =0 Bit 6 =1 =0 Bit 5 =1 =0 Bit 4 =1 =0 Bit 3 =1 =0 T06 output frequency set to 311.04 MHz * T06 output frequency set by Address 3A (5:4) (default) SONET mode selected for Dig2 SDH mode selected for Dig2 (default) - see register cnfg_T0_output_frequencies SONET mode selected for Dig1 SDH mode selected for Dig1 (default) - see register cnfg_T0_output_frequencies Output port T01 enabled (default) Output port T01 disabled** - see register cnfg_T0_output_frequencies 00011111 Output port T02 enabled (default) Output port T02 disabled** - see register cnfg_T0_output_frequencies Bit 2 =1 =0 Output port T03 enabled (19.44 MHz*) (default) Output port T03 disabled** Bit 1 =1 =0 Output port T04 enabled (38.88 MHz*) (default) Output port T04 disabled** Bit 0 =1 =0 Output port T05 enabled (77.76 MHz*) (default) Output port T05 disabled** Notes: * Defaults frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 10. ** "Disabled" means that the output port holds a static logic value (the port is not Tristated). Revision 2.02/June 2006 (c) Semtech Corp. Page 33 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 39 Register Name cnfg_T0_output_ frequencies Description Default Value (Bin) This register holds the frequency selections for each output port, as detailed below.* Bits (7:6) Dig2 00 1544 kHz/2048 kHz (default) 01 3088 kHz/4096 kHz 10 6176 kHz/8192 kHz 11 12352 kHz/16384 kHz Bits (5:4) Dig1 00 1544 kHz/2048 kHz (default) 01 3088 kHz/4096 kHz 10 6176 kHz/8192 kHz 11 12352 kHz/16384 kHz Bits (3:2) T02 00 25.92 MHz 01 51.84 MHz 10 38.88 MHz (default) 11 Dig2 Bits (1:0) T01 00 6.48 MHz (default) 01 25.92 MHz 10 19.44 MHz 11 Dig1 0000100 For Dig1/Dig2 the frequency values are shown for SONET/SDH. They are selected via the SONET/SDH bits in register cnfg_T0_output_enable. Note: * The above frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 10. 3A cnfg_differential_ outputs This register holds the frequency selections and the port-technology type for the differential outputs, T06 and T07, as detailed below. Bits (7:6) T07 00 155.52 MHz 01 51.84 MHz 10 77.76 MHz 11 19.44 MHz (default) Bits (5:4) T06 00 38.88 MHz (default) 01 19.44 MHz 10 155.52 MHz 11 Dig1 Bits (3:2)T07 00 Port disabled 01 PECL-compatible (default) 10 LVDS-compatible 11 Unused Bits (1:0) T06 00 Port disabled 01 PECL-compatible 10 LVDS-compatible (default) 11 Unused Revision 2.02/June 2006 (c) Semtech Corp. Page 34 11000110 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 3B Register Name cnfg_bandwidth cnfg_nominal_frequency Description Default Value (Bin) This register contains information used to control the operation of the digital PLL. When bandwidth selection is set to automatic, the DPLL will use the acquisition bandwidth setting when out of lock, and the normal/locked bandwidth setting when in lock. When set to manual, the DPLL will always use the normal/locked bandwidth setting. Bit 7 =1 =0 Automatic operation Manual operation (default) Bits (6:4) 000 001 010 011 100 101 110 111 Acquisition bandwidth 0.1 Hz 0.3 Hz 0.5Hz 1.0 Hz 2.0 Hz 4.0 Hz 8.0 Hz 17 Hz (default) Bit 3 Unused Bit (2:0) 000 001 010 011 100 101 110 111 Loop bandwidth 0.1 Hz 0.3 Hz 0.5 Hz 1.0 Hz 2.0 Hz 4.0 Hz (default) 8.0 Hz 17 Hz 0111X101 This register holds a 16 bit unsigned integer allowing compensation for offset of the crystal oscillator from the nominal 12.8 MHz. See "Crystal Frequency Calibration" on page 9. Default results in 0 ppm adjustment. 3C Bits (7:0) cnfg_nominal_frequency bits (7:0) 10011001 3D Bits (7:0) cnfg_nominal_frequency bits (15:8) 10011001 cnfg_holdover_offset This register holds a 19-bit signed integer, representing the holdover offset value, which can be used to set the holdover mode frequency when enabled via the holdover offset enabled bit in the cnfg_mode register. 3E Bits (7:0) cnfg_holdover_offset bits (7:0) 00000000 3F Bits (7:0) cnfg_holdover_offset bits (15:8) 00000000 40 Bit 7 =1 Auto Holdover Averaging enable. This enables the frequency average to be taken from 32 samples. One sample taken every 32 seconds, after the frequency has been confirmed to be in-band by the frequency monitors. This gives a 17 minute history of the currently locked to reference source for use in Holdover. (default). =0 Auto Holdover Averaging disabled. 1XXXX000 Bits (6:3) Unused Bits (2:0) cnfg_holdover_offset bits (18:16) Revision 2.02/June 2006 (c) Semtech Corp. Page 35 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) Register Name cnfg_freq_limit Description Default Value (Bin) This register holds a 10 bit unsigned integer representing the pull-in range of the DPLL. It should be set according to the accuracy of crystal implemented in the application, using the following formula: Frequency range (ppm) = (cnfg_freq_limit x 0.0785)+0.01647 or cnfg_freq_limit = (Frequency range (ppm) - 0.01647) / 0.0785 Default value when SRCSW is left unconnected or tied low is 9.3 ppm. Default value when SRCSW is high is the full range of around 80 ppm. 41 Bits (7:0) cnfg_freq_limit bits (7:0) 01110101 (SRCSW low) 11111111 (SRCSW high) 42 Bits (7:2) Unused XXXXXX00 (SRCSW low) XXXXXX11 (SRCSW high) Bits (1:0) cnfg_freq_limit bits (9:8) cnfg_interrupt_mask Each bit, if set to 0 will disable the appropriate interrupt source in either the interrupt status register or the sts_T4_inputs register. 43 Bits (7:0) cnfg_interrupt_mask bits (7:0) 11111111 44 Bits (7:0) cnfg_interrupt_mask bits (15:8) 11111111 45 Bits (7:5) Unused Bits (4:0) cnfg_interrupt_mask bits (20:16) XXX11111 cnfg_freq_divn This 14 bit integer is used as the divisor for any input applied to <I_14>:<I_1> to get the phase locking frequency desired. Only active for inputs with the DivN bit set to "1". This will cause the input frequency to be divided by (N+1) prior to phase comparison, e.g. program N to: ((input freq)/ 8 kHz) -1 The reference_source_frequency bits should be set to reflect the closest spot frequency to the input frequency, but must be lower than the input frequency. 46 Bits (7:0) cnfg_freq_divn bits (7:0) 00000000 47 Bits (7:6) Unused Bits (5:0) cnfg_freq_divn bits (13:8) XX000000 Revision 2.02/June 2006 (c) Semtech Corp. Page 36 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) 48 Register Name cnfg_monitors Description Default Value (Bin) This 7 bit register allows global configuration of monitors and control of phase buildout. Bit 7 Unused Bit 6 =1 Enables value of the main_ref_failed interrupt to be driven out of pin TDO =0 Disables value of the main_ref_failed interrupt from being driven out of pin TDO (default). Bit 5 =1 Enables ultra fast switching: Allows the DPLL to raise an inactivity alarm on the currently selected source after missing only a few cycles. See "Ultra Fast Switching" on page 40. =0 Normal operation (default) Bit 4 =1 Forces locking to <I_3> if pin SRCSW high, or <I_4> if SRCSW low =0 Pin SRCSW ignored and automatic control enabled. X0000101 (SRCSW low) X0010101 (SRCSW high) Bit 3 =1 Will freeze the output phase relationship with the current input to output phase offset. =0 Allows changes in input to output phase offset (Normal phase buildout mode) (default). Bit 2 =1 Enables phase build out (default). =0 DPLL will always lock to 0 Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15 ppm (default), others are reserved for future use. 50 cnfg_activ_upper_ threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be raised 51 cnfg_activ_lower_ threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be cleared 52 cnfg_bucket_size0 Bits (7:0) set the maximum value that the leaky bucket can reach given an inactive input 53 cnfg_decay_rate0 Bits (7:2)Unused Bits (1:0) control the leak rate of the leaky bucket. The fill-rate of the bucket is +1 for every 128 ms interval that has experienced some level of inactivity. The decay rate is programmable in ratios of the fill rate. The ratio can be set to 1:1, 2:1, 4:1, 8:1 by using values of 00, 01, 10, 11 respectively. However, these buckets are not "true" leaky buckets in nature. The bucket stops "leaking" when it is being filled. This means that the fill and decay rates can be the same (00 = 1:1) with the net effect that an active input can be recognized at the same rate as an inactive one. 54 cnfg_activ_upper_ threshold1 As for Reg. 50 but for bucket 1 Revision 2.02/June 2006 (c) Semtech Corp. 00000110 00000100 00001000 XXXXXX01 00000110 Page 37 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 14 Register Description (cont...) Addr. (Hex) Register Name Description Default Value (Bin) 55 cnfg_activ_lower_ threshold1 As for Reg. 51 but for bucket 1 56 cnfg_bucket_size1 As for Reg. 52 but for bucket 1 00001000 57 cnfg_decay_rate1 As for Reg. 53 but for bucket 1 XXXXXX01 58 cnfg_activ_upper_ threshold2 As for Reg. 50 but for bucket 2 59 cnfg_activ_lower_ threshold2 As for Reg. 51 but for bucket 2 5A cnfg_bucket_size2 As for Reg. 52 but for bucket 2 00001000 5B cnfg_decay_rate2 As for Reg. 53 but for bucket 2 XXXXXX01 5C cnfg_activ_upper_ threshold3 As for Reg. 50 but for bucket 3 5D cnfg_activ_lower_ threshold3 As for Reg. 51 but for bucket 3 5E cnfg_bucket_size3 As for Reg. 52 but for bucket 3 00001000 5F cnfg_decay_rate3 As for Reg. 53 but for bucket 3 XXXXXX01 7F cnfg_uPsel Bits (7:3) Unused 00000100 00000110 00000100 00000110 00000100 Bits (2:0) can be used to change the mode of the microprocessor interface. The interface will initially be set as the pins UPSEL (pins 58 - 60) - the pin set up can be read via register 37 (cnfg_uPsel_pins). At power up or reset the device will default to this setting. This register can be used to change the microprocessor mode after start up, supporting booting from EPROM and subsequently communicating via another mode. At start up the EPROM will down load the pre-programmed settings for all the registers, and as the last operation, action the change of interface with this last register. It is recommended that this function is only used for EPROM start up applications, as subsequent versions of this device may only allow operation in this way. The bits are defined in Table 11 or as given in Reg. 37 of the register map description. Revision 2.02/June 2006 (c) Semtech Corp. Page 38 Bits(7:3)= XXXXX Bits(2:0)= Pin dependent www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Also, in a Master/Slave redundancy-protection scheme, Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority. But, for special circumstances, such as chip or board testing, the selection may be forced by configuration. Automatic operation selects a reference source based on its pre-defined priority and its current availability. A table is maintained which lists all reference sources in the order of priority. This is initially downloaded into the ACS8510 Rev2.1 via the microprocessor interface by the Network Manager, and is subsequently modified by the results of the ongoing quality monitoring. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. The ACS8510 Rev2.1 has two modes of operation; Revertive and Non-Revertive. In Revertive mode, if a revalidated (or newly validated) source has a higher priority than the reference source which is currently selected, a switchover will take place. Many applications prefer to minimize the clock switching events and choose Non-Revertive mode. In Non-Revertive mode, when a revalidated (or newly validated) source has a higher priority then the selected source will be maintained. The revalidation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Selection of the re-validated source can only take place under software control - the software should briefly enable Revertive mode to affect a switchover to the higher priority source. If the selected source fails under these conditions the device will indicate that it is still locked to the failed reference. It will not select the higher priority source until instructed to do so by the software; by briefly setting the Revertive mode bit. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-Revertive mode remains on AND the device will remain indicating a locked state on the failed reference. This is the case even if there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switchover, regardless of whether Revertive or Non-Revertive mode has been chosen. Revision 2.02/June 2006 (c) Semtech Corp. the Slave device(s) must follow the Master device. The alignment of the Master and Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8510 Rev2.1 device is monitored locally and the results are made available to other devices. Forced Control Selection A configuration register, cnfg_ref_selection, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). The forced selection of an input reference source occurs when the cnfg_ref_selection variable contains a non-zero value, the value then representing the input port required to be selected. This is not the normal mode of operation, and the cnfg_ref_selection variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. Automatic Control Selection When an automatic selection is required, the cnfg_ref_selection register must be set to all zero or all one. The configuration registers, cnfg_ref_selection_priority, held in the P port block, consists of seven, 8 bit registers organised as one 4-bit register per input reference port. Each register holds a 4bit value which represents the desired priority of that particular port. Unused ports should be given the value, '0000' or '1111', in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 6. The selection priority values are all relative to each other, with lowervalued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. Page 39 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL The input port <I_11> is for the connection of the synchronous clock of the TOUT0 output of the Master device (or the active-Slave device), to be used to align the TOUT0 output with the Master (or active-Slave) device if this device is acting in a subordinate-Slave or subordinate-Master role. Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the "no activity alarm" and cause a reference switch. This can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. The sts_interrupts register 05 Hex Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If bit 6 of the cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO pin of the device. The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupt bit 14 to be reflected in the state of the TDO output pin. The pin will, therefore remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When JTAG is normally used straight out of power-up, then this feature will have no bearing on the functionality. The TDO flagging feature will need to be disabled if JTAG is not enabled on powerup and the feature has since been enabled. When the TDO output from the ACS8510 Rev2.1 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. External Protection Switching DATASHEET configures the default frequency tolerance of <I_3> and <I_4> to +/- 80 ppm (register address 41Hex and 42Hex). Any of these registers can be subsequently set by external software if required. When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. Clock Quality Monitoring Clock quality is monitored and used to modify the priority tables of the local and remote ACS8510 Rev2.1 devices. The following parameters are monitored: 1. Activity (toggling) 2. Frequency (This monitoring is only performed whenthere is no irregular operation of the clock or loss of clock condition) In addition, input ports <I_1> and <I_2> carry AMIencoded composite clocks which are monitored by the AMI-decoder blocks. Loss of signal is declared by the decoders when either the signal amplitude falls below +0.3 V or there is no activity for 1 ms. Any reference source which suffers a loss-of-signal, lossof-activity, loss-of-regularity or clock out-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behavior. Anomalies on the selected clock, therefore, have to be detected Fast external switching between inputs <I_3> and <I_4> can also be triggered directly from a dedicated pin (SRCSW). This mode can be activated either by holding this pin high during reset, or by writing to bit 4 of register address 48Hex. Once external protection switching is enabled, then the value of this pin directly selects either <I_3> (SRCSW high) or <I_4> (SRCSW low). If this mode is activated at reset by pulling the SRCSW pin high, then it Revision 2.02/June 2006 (c) Semtech Corp. Page 40 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 9 Inactivity and Irregularity Monitoring Inactivities/Irregularities Reference Source bucket_size Leaky Bucket Response upper_threshold lower_threshold Programmable Fall Slopes (all programmable) Alarm F8530D_026Inact_Irreg_Mon_02 Revision 2.02/June 2006 (c) Semtech Corp. Page 41 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains appropriate circuitry, based around the phase detector, and isolates itself from the selected reference source as soon as a signal impurity is detected. It can likewise respond to frequency offsets outside the permitted range since these result in saturation of the phase detector. When the phase locked loop is isolated from the reference source, it is essentially operating in a Holdover state; this is preferable to feeding the loop with a standby source, either temporarily or permanently, since excessive phase excursions on the output clock are avoided. Anomalies detected by the phase detector are integrated in a leaky bucket accumulator. Occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. Activity Monitoring The ACS8510 Rev2.1 has a combined inactivity and irregularity monitor. The ACS8510 Rev2.1 uses a "leaky bucket" accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 9. The "leaky bucket" accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The "fill rate" of the leaky bucket is, therefore, 8 units/second. The "leak rate" of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to "leak" at the same time as a "fill" is avoided by preventing a "leak" when a "fill" event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Frequency Monitoring The ACS8510 Rev2.1 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range of 16.6 ppm (measured with respect to the output clock). The sts_reference_sources out-of-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. The ACS8510 Rev2.1 DPLL has a programmable frequency limit of 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. Page 42 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Modes of Operation FINAL The ACS8510 Rev2.1 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and Pre-Locked2). These are shown in the State Transition Diagram, Figure 11. The ACS8510 Rev2.1 can operate in Forced or Automatic control. On reset, the ACS8510 Rev2.1 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run mode The Free-run mode is typically used following a power-onreset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8510 Rev2.1 are based on the Master clock frequency provided from the external oscillator and are not synchronized to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. The transition from Free-run to Pre-locked occurs when the ACS8510 Rev2.1 selects a reference source. reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, 'in phase', is not applied in the conventional sense when the ACS8510 Rev2.1 is used as a frequency translator (e.g., when the input frequency is 2.048 MHz and the output frequency is 19.44 MHz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. Lost_Phase mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. This mode is similar in behavior to the Pre-locked or Pre-locked(2) modes, although in this mode the DPLL is attempting to regain lock to the same reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: 1. Go to Pre-Locked(2); - If a known-good standby source is available. 2. Go to Holdover; - If no standby sources are available. Pre-Locked mode The ACS8510 Rev2.1 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Locked mode The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8510 Rev2.1 is in Locked mode, the output frequency and phase follows that of the selected input Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET Holdover mode The Holdover mode is used when the ACS8510 Rev2.1 has been in Locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection. In Holdover mode, the ACS8510 Rev2.1 provides the timing and synchronization signals to maintain the Network Element (NE), but they are not phase locked to any input reference source. The timing is based on a stored value of the frequency ratio obtained during the last Locked mode period. To allow for further development of the way the internal algorithm operates, and to allow for customized switching behavior, the switch to and from Holdover state may be controlled by external software. Page 43 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL The device must be set in either "manual" mode or "automatic" mode: 1. Register cnfg_mode bit holdover offset enable set high (manual mode). The Holdover frequency is determined by the value in register cnfg_holdover_offset. This is a 19 bit signed number, with a LSB resolution of 0.0003 ppm, which gives an adjustment range of 80 ppm. This value can be derived from a reading of the register sts_curr_inc_offset (addr 0D, 0C and 07) which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by an external microcontroller and averaged over the time required. The averaged value could then be fed to the cnfg_holdover_offset register ready for setting of the averaged frequency value when the device enters Holdover mode. The sts_curr_inc_offset value is internally derived from the Digital Phase Locked Loop (DPLL) integral path value, which already represents a well averaged measure of the current frequency, depending on the loop bandwidth selected. 2. Register cnfg_mode bit holdover offset enable set low (automatic mode). In automatic control, the device can be run in one of two ways: 2.1 Register cnfg_holdover_offset register 40 bit 7 auto holdover averaging is set high. The value is averaged internally over 32 samples at 32 seconds apart, giving the average frequency over approximately the last 20 minutes. The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. If the device has been previously correctly locked, missing pulses in the input clock stream fed to the SETS IC are ignored, hence also avoiding any frequency disturbances to the output frequency value when an input clock source fails. 2.2 Register cnfg_holdover_offset register 40 bit 7 auto holdover averaging is set low. This simply freezes the DPLL at the current frequency (as reported by the sts_curr_inc_offset register). The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. Automatic control with internal averaging (option 2.1) is the default condition. If the TCXO frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET 0.05 ppm limit (depending on how extreme the temperature fluctuations are). It is advantageous to shield the TCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Pre-Locked(2) mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. Upon applying a reference source to the phase locked loop, the ACS8510 Rev2.1 will enter the Locked state in a maximum of 100 seconds, as defined by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Holdover mode and another reference source is selected. Protection Facility The ACS8510 Rev2.1 supports redundancy protection. The primary functions of this include: - Alignment of the priority tables of both Master and Slave ACS8510 Rev2.1 devices so as to align the selection of reference sources of both Master and Slave ACS8510 Rev2.1 devices. - Alignment of the phases of the 8 kHz and 2 kHz clocks in both Master and Slave ACS8510 Rev2.1 devices to within one cycle of the 77.76 MHz internal clock. When two ACS8510 Rev2.1 devices are to be used in a redundancy-protection scheme within an NE, one will be designated as the Master and the other as the Slave. It is expected that an NE will use the TOUT0 output for its internal operations because the TOUT4 output is intended to feed an SSU/BITS system. An SSU/BITS will not be bothered by phase differences between signals arriving from different sources because it typically incorporates line build-out functions to absorb phase differences on reference inputs. This means that the phasing of the Page 44 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL composite clocks between two ACS8510 Rev2.1 devices do not have to be mutually-aligned. The same is not true, however, of the TOUT0 output signals (T01 - T07, Frame clock and Multi-Frame clock). It is usually important to align the phases of all equivalent TOUT0 signals generated by different sources so that switch-over from one device to another does not affect the internal operations of the NE. Both ACS8510 Rev2.1 devices will produce the same signals, which will be routed around the NE to the various consumers (clock sinks). With the possible exception of a through-timing mode, the signals from the Master device will be used by all consumers, unless the Master device fails, when each consumer will switch over to the signals generated by the Slave device. Switchover to a new TOUT0 clock should be as hitless as possible. This requires the signals of both ACS8510 Rev2.1 devices to be phase aligned at each consumer. Phase alignment requires frequency alignment. To ensure that both devices can generate output clocks locked to the same source, both devices are supplied with the same reference sources on the same input ports and will have identical priority tables. Failures of selected reference sources will result in both ACS8510 Rev2.1 devices making the same updates to their priority tables as availability information will be updated in both devices. Although, in principle, the priority tables will be the same if the same reference sources are used on the same input port on each device, in practice, this is only true if the reference sources actually arrive at each device - failures of a source seen only by one device and not by the other, such as could be caused, for example, by a backplane connector failure, would result in the priority tables becoming misaligned. It is thus necessary to force the priority tables to be aligned under normal operating conditions so that the devices can make the same decisions - this can be achieved by loading the availability seen by one device (via the sts_reference_sources register) into the cnfg_sts_remote_sources_valid register of the other device. Another factor which could affect hit-less switching is the frequency of the local oscillator clock used by each ACS8510 Rev2.1 device: these clocks are not mutually aligned and, whilst this has no impact on the frequency of the output clocks during locked mode, it could cause the output frequencies to diverge during Holdover mode if no action were taken to avoid it. In order to maintain alignment of the output frequencies of each ACS8510 Rev2.1 device even during Holdover, the Master device's 6.48 MHz output is fed into the Slave Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET device on its <I_11> pin, whilst the Multi-Frame Sync (2 kHz) output is fed to the Sync2k input of the Slave. In this way, the Slave locks to the master's output and remains locked whilst the Master moves between operating states. Only when the Master fails does the Slave use its own reference inputs - should the Master have been in the Holdover state, the Slave device will see the same lack of reference sources and also enter the Holdover state. This scheme also provides a convenient way to phase-align all TOUT0 output clocks in Master and Slave devices, and also to detect the failure of the Master device. If a Master device fails, the Slave has to take over responsibility for the generation of the output clocks, including the 8 kHz and 2 kHz Frame and Multi-Frame clocks. The Slave device is also given responsibility for building the priority table and performing the reference switching operations. The Slave device, therefore, adopts a more active role when the Master has failed. The cnfg_mode register 34 (Hex) Bit 1 contains the Master/Slave control bit to determine the designation of the device. To restore redundancy protection, the Master has to be repaired and replaced. When this occurs, the new Master cannot immediately adopt its normal role because it must not cause phase hits on the output clocks. It has, therefore, to adopt a subordinate role to the active Slave device, at least until such time as it has acquired alignment to the 8 kHz and 2 kHz frame and Multi-Frame clocks and the priority table of the Slave device; then, when a switch-back (restoration) is ordered, the Master can take over responsibility. These activities, in Master or Slave operation, are summarized in Table 15 and described in detail in Application Note AN-SETS-2. Alignment of Priority Tables in Master and Slave ACS8510 Rev2.1 Correct protection will only be achieved by connecting individual reference sources to the same input ports on each device and priority tables in each device must be aligned to each other. The Master device must take account of the availability of each reference source seen by another device and a Slave device must adopt the same order of priority as the Master device (except that the Slave's highest-priority input is <I_11>). Both devices monitor the reference sources and decide the availability of each source; if the failure of a reference source is seen by both devices, they will both update their priority tables - however, if the Page 45 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL reference source failure is only seen by one device and not by both, the priority tables could get out of step: this could be catastrophic if it resulted in two devices choosing different reference sources since any slight differences in frequency variation over time (e.g. wander) would misalign the phase of the 8 kHz Frame and 2 kHz MultiFrame clocks produced by the individual devices, resulting in phase hits on switch-over. It is therefore important that the same priority table be built by each device, using the reference source availability seen by each device. The monitoring of the reference sources performed by a Master ACS8510 Rev2.1 results in a list of available sources being placed in a sts_valid_sources register. This information is used within the device as one of the masks used to build the device's priority table. The information is passed to the Slave device and used to configure the cnfg_sts_remote_sources_valid register so that it can use it as a mask in building its own priority tables. The information is passed between devices using the microprocessor port. In accordance with the alignment mechanism used with the main TOUT0 clock (described in the opening paragraphs of this section), whereby the 6.48 MHz output of the Master device is supplied to the Slave device, the alignment of both the 8 kHz and 2 kHz clocks is accomplished (they are already synchronous to the TOUT0 clocks) by feeding the 2 kHz clock of the Master device into the Slave device. The MultiFrame Sync clock output of the Slave device is also fed to the Sync2K input of the Master device. Alignment of the Multi-Frame Sync input occurs only when cnfg_mode register, bit 3, address 34Hex External 2 kHz Sync Enable is set to 1. JTAG The JTAG connections on the ACS8510 Rev2.1 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support INTEST. However this does not affect board testing. Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 Rev2.1 As stated previously, there is no need to align the phases of the TOUT4 outputs in Master and Slave devices. There is a need, however, to ensure that all devices select the same reference source. But, since there is no Holdover mode required for the generation of the TOUT4 clock, and every reference source is continuously monitored within each device, it is permissible to rely on external intelligence to command a switchover to an alternative source should the selected one fail. The time delay involved in detecting the failure, indicating it to the outside and selecting a new source, will result only in the SSU/BITS entering its Holdover mode for a short time. Alignment of the Phases of the 8 kHz and 2 kHz Clocks in both Master and Slave ACS8510 Rev2.1 In addition to aligning the edges of the TOUT0 outputs of Master and Slave devices, it is necessary to align the edges of the Frame and MultiFrame clocks. If this is not performed, frame alignment may be lost in distant equipment on switch-over to an alternative device, resulting in anomalous network operation of a very serious nature. Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET 2. In common with some other manufacturers, pin TRST is internally pulled low to disable JTAG by default. The standard is to pull high. The polarity of TRST is as the standard: TRST high to enable JTAG boundary scan mode, TRST low for normal operation. 3. The device does not support the optional tri-state capability (HIGHZ). This will be supported on the next revision of the device. The JTAG timing diagram is shown in Figure 17. PORB The Power On Reset (PORB) pin resets the device if forced Low for a power on reset to be initiated. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset is required at power on, and may be re-asserted at any time to restore defaults. This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8510 Rev2.1 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. Page 46 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 10 Master-Slave Schematic Table 15 Master-Slave Relationship Ref_sources to Master ACS8510 Rev2.1 Ref_sources to Slave ACS8510 Rev2.1 Master ACS8510 Rev2.1 Status Slave ACS8510 Rev2.1 Status Master ACS8510 Rev2.1 Slave ACS8510 Rev2.1 Output All good All good Good Good Locked (ref_x) Locked to Master Some Failed Some others failed Good Good Locked (ref_y) Locked to Master Good Good Good Failed Locked (ref_x) Dead Good Good Failed Good Dead Locked (ref_x) Good Good Failed Failed Dead Dead Failed Failed Failed Good Holdover Locked to Master Failed Failed Good Failed Holdover Dead Failed Failed Failed Good Dead Holdover Failed Failed Failed Failed Dead Dead Comments Notes: (i) Both ACS8510 Rev2.1 must build a common priority table so that the Slave ACS8510 Rev2.1 can select the same input reference source as the Master ACS8510 Rev2.1 if the Master fails (when the Master is OK, the Slave locks to the Master's output). (ii) Slave ACS8510 Rev2.1 uses common priority table, built before Master ACS8510 Rev2.1 failed - priority table can be modified asstatus of the input reference sources changes. (iii) Slave ACS8510 Rev2.1 outputs must remain in phase with those of Master ACS8510 Rev2.1. Revision 2.02/June 2006 (c) Semtech Corp. Page 47 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Page 48 www.semtech.com Figure 11 Automatic Mode Control State Diagram Revision 2.02/June 2006 (c) Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Electrical Specification FINAL DATASHEET Maximum Ratings Important Note: The "Absolute Maximum Ratings"are stress ratings only, and functional operation of the device at conditions other than those indicated in the "Operating Conditions" sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 16 Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Supply Voltage VDD, VD+, VA1+, VA2+ VDD -0.5 3.6 V Input Voltage (non-supply pins) VIN - 5.5 V VOUT - 5.5 V Output Voltage (non-supply pins) TA -40 +85 o TSTOR -50 +150 o Ambient Operating Temperature Range Storage Temperature C C Operating Conditions Table 17 Operating Conditions Parameter Symbol Minimum Typical Maximum Units Power Supply (dc voltage) VDD, VD+, VA1+, VA2+, VAMI+, VDD_DIFF VDD 3.0 3.3 3.6 V Power Supply (dc voltage) VDD5 VDD5 3.0 3.3/5.0 5.5 V Ambient Temperature Range TA -40 - +85 o Supply Current (Typical - one 19 MHz output) IDD - 130 222 mA Total Power Dissipation PTOT - 430 800 mW C DC Characteristics Table 18 DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2.0 - - V VIN Low VIL - - 0.8 V Input Current IIN - - 10 A Revision 2.02/June 2006 (c) Semtech Corp. Page 49 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 19 DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Pull-up Resistor PU 30 - 80 k Input Current IIN - - 120 Table 20 DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2.0 - - V VIN Low VIL - - 0.8 V Pull-down Resistor PD 30 - 80 k Input Current IIN - - 120 A Symbol Minimum Typical Maximum Units VOUT Low (lOL = 4 mA) VOL 0 - 0.4 V VOUT High (lOH = 4 mA) VOH 2.4 - - V ID - - 4 mA Table 21 DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated Parameter Drive Current Table 22 DC Characteristics: PECL Input/Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units PECL Input Low Voltage Differential Inputs (Note ii) VILPECL VDD-2.5 - VDD-0.5 V PECL Input High Voltage Differential Inputs (Note ii) VIHPECL VDD-2.4 - VDD-0.4 V Input Differential Voltage VIDPECL 0.1 - 1.4 V VILPECL_S VDD-2.4 - VDD-1.5 V PECL Input Low Voltage Single-ended Input (Note iii) Revision 2.02/June 2006 (c) Semtech Corp. Page 50 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 22 DC Characteristics: PECL Input/Output Port (cont...) Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VILPECL_S VDD-1.3 - VDD-0.5 V Input High Current Input Differential Voltage VID = 1.4V IIHPECL -10 - +10 A Input Low Current Input Differential Voltage VID = 1.4V IILPECL -10 - +10 A PECL Output Low Voltage (Note iv) VOLPECL VDD-2.10 - VDD-1.62 V PECL Output High Voltage (Note iv) VOHPECL VDD-1.25 - VDD-0.88 V PECL Output Differential Voltage (Note iv) VODPECL 580 - 900 mV PECL Input High Voltage Single-ended Input (Note iii) Notes: (i) Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. (ii) Assuming a differential input voltage of at least 100 mV. (iii) Unused differential input terminated to VDD -1.4 V. (iv) With 50 load on each pin to VDD -2 V, i.e. 82 to GND and 130 to VDD. Figure 12 Recommended Line Termination for PECL Input/Output Ports V DD V DD 130 n x 8 kHz, 1.544/2.048 MHz, ZO=50 6.48 MHz, 19.44 MHz, 82 38.88 MHz, 51.84 MHz, 77.76 MHz or ZO=50 155.52 MHz I5POS T06POS I5NEG T06NEG 130 130 ZO=50 82 GND V DD V DD I6POS T07POS 130 ZO=50 82 130 I6NEG 130 Fully Programmable T07NEG ZO=50 82 82 GND GND V DD = +3.3 V where n = integer 1 to 12,500 Revision 2.02/June 2006 (c) Semtech Corp. Fully Programmable 82 ZO=50 GND 130 n x 8 kHz, 1.544/2.048 MHz, ZO=50 6.48 MHz, 19.44 MHz, 82 38.88 MHz, 51.84 MHz, 77.76 MHz or ZO=50 155.52 MHz 130 82 Page 51 F8530D_024PECL_03 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 23 DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VVRLVDS 0 - 2.40 V VDITH -100 - +100 mV VIDLVTSDS 0.1 - 1.4 V RTERM 95 100 105 LVDS Output High Voltage (Note (i)) VOHLVDS - - 1.585 V LVDS Output Low Voltage (Note (i)) VOLLVDS 0.885 - - V LVDS Differential Output Voltage VODLVDS 250 - 450 mV LVDS Change in Magnitude of Differential Output Voltage for complementary States (Note (i)) VDOSLVDS - - 25 mV LVDS Output Offset Voltage Temperature = 25oC (Note (i)) VOSLVDS 1.125 - 1.275 V LVDS Input Voltage Range Differential Input Voltage = 100 mV LVDS Differential Input Threshold LVDS Input Differential Voltage LVDS Input Termination Resistance Must be placed externally across the LVDS input pins of ACS8510 Rev2.1. Resistor should be 100 with 5% tolerance Note: (i) With 100 load between the differential outputs. Figure 13 Recommended Line Termination for LVDS Input/Output Ports n x 8 kHz, 1.544/2.048 MHz, ZO=50 6.48 MHz, 19.44 MHz, 100 38.88 MHz, 51.84 MHz, 77.76 MHz or ZO=50 155.52 MHz n x 8 kHz, 1.544/2.048 MHz, ZO=50 6.48 MHz, 19.44 MHz, 100 38.88 MHz, 51.84 MHz, 77.76 MHz or ZO=50 155.52 MHz ZO=50 I5POS I5NEG T06POS 100 Fully Programmable Frequency 100 Fully Programmable Frequency T06NEG ZO=50 ZO=50 I6POS I6NEG T07POS T07NEG ZO=50 where n = integer 1 to 12,500 F8530D_025LVDS_05 Revision 2.02/June 2006 (c) Semtech Corp. Page 52 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DC Characteristics: AMI Input/Output Port (Across all operating Conditions, unless otherwise stated.) The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative pulses with a peakto-peak voltage of 2.0 0.2 V. The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64 kbit/s centralized clock interface, from ITU G.703[6]. The electrical characteristics of the 64 kbit/s interface are as follows: Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability. DATASHEET There should be a symmetrical pair carrying the composite timing signal (64 kHz and 8 kHz). The use of transformers is recommended. Over-voltage protection requirement: refer to Recommendation K.41[16] Code conversion rules: The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals convey the 64 kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the 8 kHz octet phase information by introducing violations in the code rule. The structure of the signals and voltage level are shown in Figure 14, Figure 15 and Figure 16. Table 24 DC Characteristics: AMI Input/Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units Input Pulse Width tPW 1.56 7.8 14.04 s Input Pulse Rise/Fall Time tR/F - - 5 s AMI Input Voltage High VIH AMI 2.5 - VDD + 0.3 V AMI Input Voltage Middle VVIM AMI 1.5 1.65 1.8 V AMI Input Voltage Low VVIL AMI 0 - 1.4 V AMI Output Current Drive IAMIOUT - - 20 mA AMI Output High Voltage Output Current = 20mA VOH AMI VDD - 0.16 - - V AMI Output Low Voltage Output Current = 20mA VOL AMI - - 0.16 V Nominal Test Load Impedance RTEST - 110 - "Mark" Amplitude After Transformer VMARK 0.9 1.0 1.1 V "Space" Amplitude After Transformer VSPACE - 0.1 0 0.1 V Revision 2.02/June 2006 (c) Semtech Corp. Page 53 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 14 Signal Structure of 64 kHz/8 kHz Central Clock Interface) 6 Bit Number 7 8 1 2 3 4 5 6 7 8 1 2 Timing Violation Violation Octet Start Octet Start 15.6 us 7.8 us +1.0 VIH 1V 2 V p-p 0 VIM 1V -1.0 VIL F8530D_019SigStrucCCI_01 Note...after suitable input/output transformer (also see G.703[6]). Figure 15 AMI Input and Output Signal Levels 15.6 us Signal structure of 64 kHz/8 kHz central clock interface after suitable transformer. 7.8 us +VDD 15.6 us 7.8 us 0V +1.0 VIH I1 2 V p-p T08POS C1 1V 0 VIM C2 15.6 us 1V -1.0 VIL I2 T08NEG 7.8 us +VDD C1 0V F8530D_020AMIIPandOPSigLevels_02 Revision 2.02/June 2006 (c) Semtech Corp. Page 54 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 16 Recommended Line Termination for AMI Output/Output Ports Turns ratio 3:1 AMI input signal I1 C1 Rload C2 AMI input signal I2 AMI output signal to external devices TO8POS C3 GND TO8NEG C1 F8530D_023AMI_lineterm_04 Note...The AMI inputs I1 and I2 should be connected to the external AMI clock source by 470 nF coupling capacitor C1. The AMI differential output T08POS/T08NEG should be coupled to a line transformer with a turns ratio of 3:1. Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider Rload must be used to achieve the required 1 V p-p voltage level for the positive and negative pulses. Jitter Performance Table 25 DC Characteristics: Output Jitter Generation (Test Definition G.813) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition [11] Filter used UI Spec UI Measurement on ACS8510 Rev2.1 for 155 MHz option 1 500 Hz to 1.3 MHz UIp-p = 0.5 0.058 (Note (ii)) G813[11] for 155 MHz option 1 65 kHz to 1.3 MHz UIp-p = 0.1 0.048 (Note (iii) 0.048 (Note (ii)) G813 0.053 (Note (iv)) 0.053 (Note (v)) 0.058 (Note (vi)) 0.053 (Note (vii)) G813 [11] for 155 MHz option 2 12 kHz to 1.3 MHz UIp-p = 0.1 0.053 (Note (ii)) 0.058 (Note (iii)) 0.057 (Note (viii)) 0.055 (Note (ix)) 0.057 (Note (x)) 0.057 (Note (xi)) 0.057 (Note (xii)) 0.053 (Note (xiii)) G813[11] and G812[10] for 2.048 MHz option 1 20 Hz to 100 kHz Revision 2.02/June 2006 (c) Semtech Corp. UIp-p = 0.5 Page 55 0.046 (Note (xiv)) www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 26 DC Characteristics: Output Jitter Generation (Test Definition G812) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 G812[10] for 1.544 MHz 10 Hz to 40 kHz G812[10] for 155.52 MHz electrical 500 Hz to 1.3 MHz UIp-p = 0.5 0.058 (Note (xv)) G812[10] for 2.048 MHz 65 Hz to 1.3 MHz 0.036 (Note (xv)) UIp-p = 0.05 UIp-p = 0.075 0.036 (Note (xiv)) Table 27 DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 ETS-300-462-3[3] for 2.048 MHz SEC 20 Hz to 100 kHz UIp-p = 0.5 0.046 (Note (xiv)) ETS-300-462-3[3] for 2.048 MHz SEC (Filter spec 49 Hz to 100 kHz) 20 Hz to 100 kHz UIp-p = 0.2 0.046 (Note (xiv)) ETS-300-462-3[3] for 2.048 MHz SSU 20 Hz to 100 kHz UIp-p = 0.05 0.046 (Note (xiv)) ETS-300-462-3[3] for 155.52 MHz 500 Hz to 1.3 MHz UIp-p = 0.5 0.058 (Note (xv)) ETS-300-462-3[3] for 155.52 MHz 65 kHz to 1.3 MHz UIp-p = 0.1 0.048 (Note (xv)) Table 28 DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 GR-253-CORE[17] net i/f, 51.84 MHz 100 Hz - 0.4 MHz UIp-p = 1.5 0.022 (Note (xv)) GR-253-CORE[17] net i/f, 51.84 MHz (Filter spec 20 kHz to 400 Hz) 18 kHz - 0.4 MHz UIp-p = 0.15 0.019 (Note (xv)) GR-253-CORE[17] net i/f, 155.52 MHz 500 Hz - 1.3 MHz UIp-p = 1.5 0.058 (Note (xv)) GR-253-CORE[17] net i/f, 155.52 MHz 65 kHz - 1.3 MHz UIp-p = 0.15 0.048 (Note (xv)) GR-253-CORE[17] cat II elect i/f, 155.52 MHz 12 kHz - 400 kHz UIp-p = 0.1 0.057 (Note (xv)) UIrms= 0.1 0.006 (Note (xv)) UIp-p = 0.1 0.057 (Note (xv)) UIrms= 0.01 0.006 (Note (xv)) UIp-p = 0.1 0.036 (Note (xiv)) UIrms= 0.01 0.0055 (Note (xiv)) GR-253-CORE[17] cat II elect i/f, 51.84 MHz GR-253-CORE[17] DS1 i/f, 1.544 MHz Revision 2.02/June 2006 (c) Semtech Corp. 12 kHz - 1.3 MHz 10_Hz - 40 kHz Page 56 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 29 DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 AT&T 62411[2] for 1.544 MHz (Filter spec 10Hz to 8 kHz) 10 Hz to 40 kHz UIrms = 0.02 0.0055 (Note (xiv)) AT&T 62411[2] for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (Note (xiv)) 10 Hz to 40 kHz UIrms = 0.025 0.0055 (Note (xiv)) Broadband UIrms = 0.05 0.0055 (Note (xiv)) AT&T 62411 [2] for 1.544 MHz AT&T 62411[2] for 1.544 MHz Table 30 DC Characteristics: Output Jitter Generation (Test Definition G.742) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 G-742[8] for 2.048 MHz DC to 100 kHz UIp-p = 0.25 0.047 (Note (xiv)) G-742[8] for 2.048 MHz (Filter spec 18 kHz to 100 kHz) 20 Hz to 100 kHz UIp-p = 0.05 0.046 (Note (xiv)) G-742[8] for 2.048 MHz 20 Hz to 100 kHz UIp-p = 0.05 0.046 (Note (xiv)) Table 31 DC Characteristics: Output Jitter Generation (Test Definition GR-499-CORE) Across all operating conditions unless otherwise stated Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Test Definition Filter used UI Spec UI Measurement on ACS8510 Rev2.1 GR-499-CORE[18] & G824[14] for 1.544 MHz 10 Hz to 40 kHz UIp-p = 5.0 0.036 (Note (xiv)) GR-499-CORE[18] & G824[14] for 1.544 MHz (Filter spec 8 kHz to 40 kHz) 10 Hz to 40 kHz UIp-p = 0.1 0.036 (Note (xiv)) GR-499-CORE[18] for 1.544 MHz >10 Hz UIp-p = 0.05 0.036 (Note (xiv)) Revision 2.02/June 2006 (c) Semtech Corp. Page 57 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Notes for Tables 25 to 31 Notes: (i) Filter used is that defined by test definition unless otherwise stated (ii) 5 Hz bandwidth, 19.44 MHz direct lock (iii) 5 Hz bandwidth, 8 kHz lock (iv) 20 Hz bandwidth, 19.44 MHz direct lock (v) 20 Hz bandwidth, 8 kHz lock (vi) 10 Hz bandwidth, 19.44 MHz direct lock (vii) 10 Hz bandwidth, 8 kHz lock (viii) 2.5 Hz bandwidth, 19.44 MHz direct lock (ix) 2.5 Hz bandwidth, 8 kHz lock (x) 1.2 Hz bandwidth, 19.44 MHz direct lock (xi) 1.2 Hz bandwidth, 8 kHz lock (xii) 0.6 Hz bandwidth, 19.44 MHz direct lock (xiii) 0.6 Hz bandwidth, 8 kHz lock (xiv) 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input (xv) 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input Figure 17 JTAG Timing tCYC TCK tSUR tHT TMS TDI tDOD TDO F8110D_022JTAGTiming_01 Table 32 JTAG Timing (for use with Figure 17) Parameter Symbol Minimum Typical Maximum Units Cycle Time tCYC 50 - - ns TMS/TDI to TCK rising edge time tSUR 3 - - ns TCK rising to TMS/TDI hold time tHT 23 - - ns tDOD - - 5 ns TCK falling to TDO valid Revision 2.02/June 2006 (c) Semtech Corp. Page 58 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Input/Output Timing FINAL DATASHEET Figure 18 Input/Output Timing with Phase Build-out Off Revision 2.02/June 2006 (c) Semtech Corp. Page 59 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Motorola Mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus as parallel data + address. Figure 19 and Figure 20 show the timing diagrams of read and write accesses for this mode. Figure 19 Read Access Timing in MOTOROLA Mode tpw1 CSB tsu2 WRB th2 X X th1 tsu1 A X address X td1 AD Z data td2 RDY (DTACK) td3 tpw2 th3 Z td4 Z Z F8110D_007ReadAccMotor_01 Table 33 Read Access Timing in MOTOROLA Mode (for use with Figure 19) Symbol Note: Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - td1 Delay CSBfalling edge to AD valid - - 177 ns td2 Delay CSBfalling edge to DTACKrising edge - - 13 ns td3 Delay CSBrising edge to AD high-Z - - 0 ns td4 Delay CSBrising edge to RDY high-Z - - 9 ns - - 310 ns - 472 ns ns(i) tpw1 CSB Low time tpw2 RDY High time th1 Hold A valid after CSBrising edge 0 ns - - th2 Hold WRB valid after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 320 ns - - 485 (i) Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.02/June 2006 (c) Semtech Corp. Page 60 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 20 Write Access Timing in MOTOROLA Mode tpw1 CSB tsu2 WRB th2 X X th1 tsu1 A X address X tsu3 AD data X td2 RDY (DTACK) th4 tpw2 th3 X td4 Z Z F8110D_008WriteAccMotor_01 Table 34 Write Access Timing in MOTOROLA Mode (for use with Figure 20) Symbol Note: Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - tsu3 Setup AD valid before CSBrising edge 3 ns - - td2 Delay CSBfalling edge to RDYrising edge - - 13 ns td4 Delay CSBrising edge to RDY High-Z - - 7 ns tpw1 CSB Low time 485 ns(i) - - tpw2 RDY High time 310 ns - 472 ns th1 Hold A valid after CSBrising edge 3 ns - - th2 Hold WRB Low after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - th4 Hold AD valid after CSBrising edge 4 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 320 ns - - (i) Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.02/June 2006 (c) Semtech Corp. Page 61 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Intel Mode In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data + address. Figure 21 and Figure 22 show the timing diagrams of read and write accesses for this mode. Figure 21 Read Access Timing in INTEL Mode CSB WRB tpw1 tsu2 th2 RDB th1 tsu1 A address td1 td4 Z data AD td3 td2 tpw2 th3 td5 Z RDY F8110D_009ReadAccIntel_01 Table 35 Read Access Timing in INTEL Mode (for use with Figure 21) Symbol Note: Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD valid - - 177 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge - - 14 ns td4 Delay RDBrising edge to AD high-Z - - 10 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns - - 310 ns - 472 ns (i) tpw1 RDB Low time 486 ns tpw2 RDY Low time th1 Hold A valid after RDBrising edge 0 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp Time between consecutive accesses (RDBrising edge to RDBfalling edge, or RDBrising edge to WRBfalling edge) 320 ns - - (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.02/June 2006 (c) Semtech Corp. Page 62 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 22 Write Access Timing in INTEL Mode CSB tpw1 tsu2 th2 WRB RDB tsu1 th1 address A tsu3 th4 data AD td3 td2 RDY tpw2 th3 td5 Z Z F8110D_010WriteAccIntel_01 Table 36 Write Access Timing in INTEL Mode (for use with Figure 22) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Setup AD valid before WRBrising edge 3 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 14 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 WRB Low time 486 ns(i) - - tpw2 RDY Low time 310 ns - 472 ns - - ns(ii) th1 Hold A valid after WRBrising edge th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 Hold AD valid after WRBrising edge 4 ns - - tp Time between consecutive accesses (WRBrising edge to WRBfalling edge, or WRBrising edge to RDBfalling edge) 320 ns - - 170 Notes: (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns. (ii) Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge. Revision 2.02/June 2006 (c) Semtech Corp. Page 63 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Multiplexed Mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/data bus. Figures 23 and 24 show the timing diagrams of read and write accesses. Figure 23 Read Access Timing in MULTIPLEXED Mode tpw3 tp1 ALE tsu1 th1 CSB tsu2 WRB tpw1 th2 RDB td1 address AD X td2 RDY td4 data td3 tpw2 X th3 td5 Z Z F8110D_011ReadAccMultiplex_01 Table 37 Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) Symbol Note: Parameter MIN TYP MAX tsu1 Setup AD address valid to ALEfalling edge 2 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD data valid - - 177 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge - - 15 ns td4 Delay RDBrising edge to AD data high-Z - - 9 ns td5 Delay CSBrising edge to RDY high-Z - - 10 ns - - ns(i) tpw1 RDB Low time tpw2 RDY Low time 310 ns - 472 ns tpw3 ALE High time 2 ns - - th1 Hold AD address valid after ALEfalling edge 3 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp1 Time between ALEfalling edge and RDBfalling edge 0 ns - - tp2 Time between consecutive accesses (RDBrising edge to ALErising edge) 320 ns - - 487 (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.02/June 2006 (c) Semtech Corp. Page 64 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Figure 24 Write Access Timing in MULTIPLEXED Mode tpw3 tp1 ALE tsu1 th1 CSB tsu2 th2 tpw1 WRB RDB tsu3 address AD X td2 RDY th4 data td3 tpw2 X th3 td5 Z Z F8110D_012WriteAccMultiplex_01 Table 38 Write Access Timing in MULTIPLEXED Mode (For use with Figure 24) Symbol Note: Parameter MIN TYP MAX tsu1 Set up AD address valid to ALEfalling edge 2 ns - - tsu2 Set up CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Set up AD data valid to WRBrising edge 3 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 15 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 WRB Low time 487 ns(i) - - tpw2 RDY Low time 310 ns - 472 ns tpw3 ALE High time 2 ns - - th1 Hold AD address valid after ALEfalling edge 3 ns - - th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 AD data hold valid after WRBrising edge 4 ns - - tp1 Time between ALEfalling edge and WRBfalling edge 0 ns - - tp2 Time between consecutive accesses (WRBrising edge to ALErising edge) 320 ns - - (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.02/June 2006 (c) Semtech Corp. Page 65 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Serial Mode In Serial mode, the device is configured to interface with a serial microprocessor bus. The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. Figure 25 Read Access Timing in SERIAL Mode CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0) = SDI R/W tpw1 A0 A1 A2 A3 A4 A5 A6 td1 AD(0)=SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 ALE=SCLK _ A(0)=SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 AD(0)=SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 F8530D_013ReadAccSerial_01 Revision 2.02/June 2006 (c) Semtech Corp. Page 66 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Table 39 Read Access Timing in SERIAL Mode (For use with Figure 25) Symbol Parameter MIN TYP MAX 0 ns - - 160 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge td1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 17 ns td2 Delay CSBrising edge to SDO high-Z - - 10 ns tpw1 SCLK Low time CLKE = 0 CLKE = 1 - - 250 ns 500 ns tpw2 SCLK High time CLKE = 0 CLKE = 1 - - 250 ns 500 ns th1 Hold SDI valid after SCLKrising edge 170 ns - - th2 Hold CSB Low after SCLKrising edge, for CLKE = 0 Hold CSB Low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Figure 26 Write Access Timing in SERIAL Mode CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0)=SDI AD(0)=SDO R/W tpw1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Output not driven, pulled low by internal resistor F8110D 014W it A S i l 02 Table 40 Write Access Timing in SERIAL Mode (For use with Figure 26) Symbol Parameter MIN TYP MAX 0 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - tpw1 SCLK Low time 180 ns - - tpw2 SCLK High time 180 ns - - th1 Hold SDI valid after SCLKrising edge 170 ns - - th2 Hold CSB Low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Revision 2.02/June 2006 (c) Semtech Corp. Page 67 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET EPROM Mode This mode is suitable for use with an EPROM, in which configuration data is stored (one-way communication - status information will not be accessible). A state machine internal to the ACS8510 Rev2.1 device will perform numerous EPROM read operations to read the data out of the EPROM. In EPROM Mode, the ACS8510 Rev2.1 takes control of the bus as Master and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns) after device set-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Figure 27 shows the access timing of the device in EPROM mode. Further information can be found in the AMD AM27C64 datasheet. Figure 27 Access Timing in EPROM mode CSB (=OEB) address A tacc AD Z Z data F8110D_015ReadAccEEPROM_01 Table 41 Access Timing in EPROM mode (For use with Figure 27) Symbol tacc Parameter Delay CSBfalling edge or A change to AD valid Revision 2.02/June 2006 (c) Semtech Corp. Page 68 MIN TYP MAX - - 920 ns www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Package Information FINAL DATASHEET Figure 28 LQFP Package Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Revision 2.02/June 2006 (c) Semtech Corp. Page 69 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Page 70 www.semtech.com Figure 29 Typical 100 Pin LQFP Footprint Revision 2.02/June 2006 (c) Semtech Corp. ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Application Information FINAL DATASHEET Figure 30 Simplified Application Schematic VDD IC2 VDD5v P1 VDD2 Need to update fig for ACS8510 Rev2.1 EZ1086CT-3.3 3 5v 0v VDD3 2 VIN VOUT 1 VDDA GND (+) (+) term_connect 100uF C2 Power supply and ground connections to 'star' connect back to these decoupling capacitors at the regulator and only connect together at this point C7 100nF C4 100nF 10uF_TANT C3 AGND DGND3 ZD1 BZV90C-5.6v Optional EPROM interface selection Optional Processor/EPROM interface type selection DGND2 DGND Decoupling capacitor, C21 should be placed close to the xtal pins that are being decoupled RDY RDB CSB ALE WRB Int CC parts are easily cut links that can also take SM capacitors or Ohm resistor links. SrSwit All tcxo options to be placed as close as possible to IC1, with short output track. O1 O2 VDD O3 O4 C29 C9 VDDA O5 100nF 100nF O9 DGND AGND C10 100nF AGND R1 X1 10R 2 vdd output 1 VDD3 gnd2 5 C11 100nF C21 4 optn VDDA R6 DGND3 10R C12 100nF 3 gnd1 Vectron AGND DGND VDD2 C6 100nF C5 AGND TRST IC1 IC2 AGND1 VA1+ TMS INTREQ TCK REFCLK DGND1 VD1+ VD3+ DGND3 DGND2 VD2+ IC3 SRCSW VA2+ AGND2 TDO IC4 TDI I1 I2 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGNDd VDDd UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 IC1 ACS8520 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFFa VDD_DIFFa TO6POS TO6NEG TO7POS TO7NEG GND_DIFFb VDD_DIFFb I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGNDa VDDa VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C8 1nF DGND VDD 100nF C13 DGND Optional UPSEL0 Processor UPSEL1 interface type UPSEL2 selection 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 txco 12.8MHz AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 DGNDc VDDc VDDb DGNDb TO1 TO2 TO3 VA3+ AGND3 TO4 TO5 TO9 IC5 IC6 IC7 MSTSLVB SONSDHB VDD 100nF All decoupling capacitors, C29, C9, C13, C14, C15, C6, C5, C12, C11, C10,C32 should be placed close to the IC1 pins that are being decoupled 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DGND (+) 10uF_TANT VDD DGND2 C14 100nF DGND VDD2 VDD2 C15 C32 100nF 100nF DGND2 DGND2 C23 100n 9 7 T1 4 6 Pe-68865 R41 optn C16 C17 R38 470nF 470nF I1 I2 optn optn C22 O8P DGND2 I4 I3 DGND I10 I8 I7 I9 I12 I11 I14 I13 DGND F8520D_031EvalBdSchem_01 Revision 2.02/June 2006 (c) Semtech Corp. Page 71 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Abbreviations AMI APLL BITS DFS DPLL DS1 DTO E1 I/O LOF LOS LQFP LVDS MTIE NE OCXO PBO PDH PECL PFD PLL POR ppb ppm p-p R/W rms RO RoHS SDH SEC SETS SONET SSF SSU STM TDEV TCXO UI WEEE FINAL References Alternate Mark Inversion Analogue Phase Locked Loop Building Integrated Timing Supply Digital Frequency Synthesis Digital Phase Locked Loop 1544 kb/s interface rate Discrete Time Oscillator 2048 kb/s interface rate Input - Output Loss of Frame Alignment Loss Of Signal Low profile Quad Flat Pack Low Voltage Differential Signal Maximum Time Interval Error Network Element Oven Controlled Crystal Oscillator Phase Build-out Plesiochronous Digital Hierarchy Positive Emitter Coupled Logic Phase and Frequency Detector Phase Locked Loop Power-On Reset parts per billion parts per million peak-to-peak Read/Write root-mean-square Read Only Restrictive Use of Certain Hazardous Substances (directive) Synchronous Digital Hierarchy SDH/SONET Equipment Clock Synchronous Equipment Timing source Synchronous Optical Network Synchronization Signal Failure Synchronization Supply Unit Synchronous Transport Module Time Deviation Temperature Compensated Crystal Oscillator Unit Interval Waste Electrical and Electronic Equipment (directive) Revision 2.02/June 2006 (c) Semtech Corp. DATASHEET [1] ANSI T1.101-1999 (1999) Synchronization Interface Standard [2] AT & T 62411 (12/1990) ACCUNET(R) T1.5 Service description and Interface Specification [3] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 3: The control of jitter and wander within synchronization networks [4] ETSI ETS 300 462-5 (09/1996) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment [5] IEEE 1149.1 (1990) Standard Test Access Port and Boundary-Scan Architecture [6] ITU-T G.703 (10/1998) Physical/electrical characteristics of hierarchical digital interfaces [7] ITU-T G.736 (03/1993) Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s [8] ITU-T G.742 (1988) Second order digital multiplex equipment operating at 8448 kbit/s, and using positive justification [9] ITU-T G.783 (10/2000) Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks [10] ITU-T G.812 (06/1998) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks [11] ITU-T G.813 (08/1996) Timing characteristics of SDH equipment slave clocks (SEC) [12] ITU-T G.822 (11/1988) Controlled slip rate objectives on an international digital connection [13] ITU-T G.823 (03/2000) The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Page 72 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS FINAL DATASHEET Trademark Acknowledgements [14] ITU-T G.824 (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. [15] ITU-T G.825 (03/2000) The control of jitter and wander within digital networks which are based on the Synchronous Digital Hierarchy (SDH) ACCUNET(R) is a registered trademark of AT & T. [16] ITU-T K.41 (05/1998) Resistibility of internal interfaces of telecommunication centres to surge overvoltages AMD is a registered trademark of Advanced Micro Devices, Inc. Vectron is a registered trademark of Vectron International [17] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria ICT Flexacom is a registered trademark of ICT Electronics. [18] Telcordia GR-499-CORE, Issue 2 (12/1998) Transport Systems Generic Requirements (TSGR) Common requirements Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of the Intel Corporation Telcordia is a registered trademark of Telcordia Technologies. [19] Telcordia GR-1244-CORE, Issue 2 (12/2000) Clocks for the Synchronized Network: Common Generic Criteria Revision 2.02/June 2006 (c) Semtech Corp. Page 73 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Revision Status/History FINAL The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL status after DATASHEET the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release (Revision 2.02) of the ACS8510 Rev2.1 datasheet. Changes made for this document revision are given in Table 42, together with a brief summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the datasheet. Table 42 Revision History Revision 1.06 to 2.00 September 2003 Reference Description of changes Non-revertive Mode p36-37 Updated description of Non-Revertive Mode 2.01 September 2004 All pages Document reformatted, no technical changes. 2.02 June 2006 Front page, back page and "Abbreviations" on page 72 Updated to reflect availability of lead (Pb)-free packaged part. Trademark Acknowledgements and Revision Status/History Sections updated. Back page Former US mailing address removed. (Mail now delivered to main address). Figure 28 and Figure 29 Updated Package and Footprint drawings. Back page Taiwan address updated. Revision 2.02/June 2006 (c) Semtech Corp. Page 74 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Notes Revision 2.02/June 2006 (c) Semtech Corp. FINAL DATASHEET Page 75 www.semtech.com ACS8510 Rev2.1 SETS ADVANCED COMMUNICATIONS Ordering Information FINAL DATASHEET Table 43 Parts List Part Number Description ACS8510 Rev2.1 SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements ACS8510 Rev2.1T Lead (Pb)-free packaged version of ACS8510 Rev2.1; RoHS and WEEE compliant. Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications, and is not authorized or warranted for such use. Right to change- Changes may be made to this product without notice. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contact Information for Semtech International AG Taiwan Branch Korea Branch Shanghai Office Tel: 886-2-2748-3380 Fax: 886-2-2748-3390 Tel: 82-2-527-4377 Fax: 82-2-527-4376 Tel: 86-21-6391-0830 Fax: 86-21-6391-0831 Semtech International AG is a wholly-owned subsidiary of Semtech Corporation, which has its headquarters in the U.S.A. Semtech Switzerland GmbH Japan Branch Tel: 81-3-6408-0950 Fax: 81-3-6408-0951 Semtech Limited (U.K.) Tel: 44-(0)1794-527-600 Fax: 44-(0)1794-527-601 Semtech France SARL Tel: 33-(0)169-28-22-00 Fax: 33-(0)169-28-12-98 Semtech Germany GmbH Tel: 49-(0)8161-140-123 Fax: 49-(0)8161-140-124 ISO9001 CERTIFIED Revision 2.02/June 2006 (c) Semtech Corp. Page 76 www.semtech.com