MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION / @ Timers rrsrrrrrtete tet cete teens ee een et eee test nenetenteeeeenees 8-bitX6 The 3818 group is 8-bit microcomputer based on the 740 @ Serial Oe rrrerr cree rreeeeeeeee Clock-synchronized 8-bitX 2 family core technology. (Serial 1/01 has an automatic data transfer function) The 3818 group is designed mainly for VCR timer/function @ PWM output Circuit-:--------- ree reee cere ee centre 14-bitx1 control, and include six 8-bit timers, a fluorescent display 8-bitX 1 (also functions as timer 6) automatic display circuit, a PWM function, and an 8-channel @ A-D converter--------- leeneteeeeeeeeeseeeeneeses 8-bitX8 channets A-D converter. @ Fluorescent display function The various microcomputers in the 3818 group include Segments ---r-vvvvccescsrereetseeeeeeesee ere eeeeeteeteneeeeene 8 to 24 variations of internal memory size and packaging. For de- Digits vs1-vrrccrceecte ete ct ete t teeters eee nee treet ete teernes 4to 16 tails, refer to the section on part numbering. @ 2 Clock generating circuit Clock (Xin-Xour) sore Internal feedback resistor FEATURES Sub-clock (Xein-Xcour) *** Without internal feedback resistor Basic machine-language instructions ---:----7--11++--+ 71 @ Power source voltage --ttttteresrrterrt rere 4.0 to .5V @ The minimum instruction execution time--:-+-------- 0.48us @ Low power dissipation (at 8.4MHz oscillation frequency) In high-speed mode ----+--++-12-rereeeeer eet ttttteeee teens 50mw @ Memory size (at 8.4MHz oscillation frequency) ROM Sader renee eect sates eee eset earacwerenenemasee 4K to 60K bytes In low-speed mode eee eee rere eee eee eee eres 300uW RAM rirrtrectesteseetees eters creteeretetenterees 192 to 1024 bytes (at 32kHz oscillation frequency) Programmable input/output ports ------+-+-+-+6eere rere 67 @ Operating temperature range --::----+--+------- 10 to 85C @ High-breakdown-voltage I/O POMtS creeeete treet eteeeeeeeteeee 12 High-breakdown-voltage output ports <--------1 eee 20 APPLICATIONS @ Interrupts sores e rete cette tee e ee eeeeeee 18 sources, 15 vectors VCRs, microwave ovens, domestic appliances, ECRs, etc. PIN CONFIGURATION (TOP VIEW) GSITTISTS aqagagcaaqga SSSR Us OMe Te RA PENN ORG BUR ROR CRO RU RU UR RUB URORU RGR US UMC MUmUMCMURG] WHOWUWNWNWHHMMtooHBeHSe rer restos HANNVNHNNHYNHAHNHOHNHNNOABAQGGQGGAADA SERPS PPEPSAP SP Pees aes eRe Cr NOTE SEELLRIKLLRRLK RK KELRERRELAAATE tititti ttt tittttrtr+ttrr+rtritties SEVERE TERR) BIEIRIEIG EB IIBIEI REE P&87/SEG; + Bi) - Pig P&/SEGs + [2] O ~ Pl; P8s5/SEGs + [a3] + P25 P8,/SEG, = [a4 + P2; P83/SEG3 + [65] + P22 P82/SEG2 + [Be] > P23 P8,/SEG, + [a] = Py P&/SEGo <> [as] ~- P25 Vee [69] : ++ P26 PB, ~ [oo] > P27 Vcc i] M38184M8-XXXFP Vsg PBo [92] Xour AVss [93] > Xw Pp? Maer ze Xcour vOAN. Xow P7/ANg = [25] + RESET P75/AN5 [a7] P4o/INTo P74/ANg [a] ++ P4)/INT; P73/ANs ++ [3] 2+ P4:/INT2 P72/AN2 + [ia] + P43/INTS Stee eMa-Te TENS SEIS EIETeIEls Ulalteilelialeits Petter sett tert ttt ttt ttt ttt tt FRSPR ESE CESS OTP NT PR ever oOrabbtws eeieged 5s add de ei ETES ESE PZ 3 aTy Tees eRe Zee eee Pee woo eaxoere a aad gra gorgrad > a c r B a Package type : 100P6S-A 100-pin plastic molded QFP MM 6249826 0024035 27] nie 29MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER d vod yndjno td uod oO Sd vod Of 9d vod O/F ___. 7 au A SSay aww __. Kwa _-~ eo _s LNISLNI d Hod O/ td uod O/| sevkg ze 1}}0.4U00 Wi 28jsue4, oqewone O/IS 481}04j003 - ABiasip Od uod jndyno opewoyne ons dd uod O/I sng Beq 8d Hod O/ 6d vod of 13s3y ynidul josey Yd uod O/1 = dd Hod jndu| ynouio ' ' ' ' ' ' ' 1 ' t l ' ' Niy ANdyno induy yndyno jnduyy 42019 YOO]D YOOID 49019 -qng -qng 49018 TVNOLLONNA (v-S9d00L) NNVHDVIG MB 6249428 COeuo3b 108 2390PIN DESCRIPTION MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Pin Name Function Function except a port function Voc: Vsg | Power source * Apply voitage of 4.0 to 5.5V to Voc, and OV to Vss. Vee Pull-down power * Applies voltage supplied to pull-down resistors of ports PO, P3 and P9. input Veer Analog reference * Reference voltage input pin for A-D converter. voltage input AVss Analog power source * GND input pin for A-D converters * Connect to Vss. RESET Reset input Reset input pin for active L Xin Clock Input Input and output signals for the clock generating circuit. * It consist of internal feedback resistor. Xour Clock output + Connect a ceramic resonator or quartz-crystal oscillator between the Xiq and Xour pins to set the oscillation frequency. If an external clock is used, connect the clock source to the Xin pin and leave the Xour pin open. * This clock is used as the oscillating source of system clock. Xen Sub-clock input * (nput and output signals for the internal sub-clock generating circuit. * It consist of without internat feedback resistor. Connect a ceramic resonator or quartz-crystat oscillator and external feedback resistor between the Xciw and Xcour pins. Xcour Sub-clock output * If an external clock is used, connect the clock source to the Xcin pin and leave the Xcour pin open. * This clock can also be used as the oscillating source of system clock. P0,/DIGg} Output port PO * 8-bit output port * FLD automatic display pins PO;/DIGys * The output structure Is high-breakdown-voltage P- channet open drain with internal pull-down resistors connected between the output and the Vee pin. * Vee pin level is output at reset. PlgP17 (40 port P1 * 8-bit CMOS I/O port * V/O direction register allows each pin to be individually programmed as either input or output. * At reset this port is set to input mode. * CMOS compatible input level * CMOS 3-state output structure P2)P2, 1/0 port P2 + 8-bit CMOS 1/0 port with the same function as port P1 * CMOS 3-state output structure * TTL compatible input level P3,/SEGje/ | Output port P3 + 8-bit output port with the same function as port PO * FLD automatic display pins OIG,P3,/ SEG29/DIG, P4o/INTp Input port P45 * 1-bit CMOS input port * External interrupt input pin P4,/INT, | I/O port P4 * 7-bit CMOS 1/0 port with the same function as port P1 * External interrupt input pins P4,/INT, * CMOS compatible input level P4, P46/T1 our, * Timer 1, Timer 3 output pin P4;/T3out Me 6249828 0024037 O44 mm MITSUBISHI 2-391MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin Name Function Function except a port function P50/Sint, 1/O port PS * 8-bit 1/O port with the same function-as port P1 * Serial 1/01 1/0 pins P5,/Souti, * N-channel open drain output structure P52/Soiki1 * CMOS compatible input level P5s/Spovi/ * Keep the input voltage of this port between OV and Vcc. CS/Scuxi2 P54/Sinas * Seriat 1/02 1/0 pins Ps/Soura, P5e/Scixz, P57/Sppvz P6o/PWMo | 1/0 port P6 * 8-bit CMOS I/O port with the same function as port P1 * 14-bit PWM output pin * GMOS compatible input level 5 P6,/PWM; * CMOS 3-state output structure 8-bit PWM output pin P62/CNTRo, * Timer 2, Timer 4 input pins P63/CNTR, . P6, P67 P79/ANg ; 1/0 port P7 * 8-bit CMOS 1/0 port with the same function as port P1 * A-D converter input pins P77/AN7 * CMOS compatible input level CMOS 3-state output structure P8/SEGo | 1/0 port P8 * 8-bit I/O port with the same function as port P1 * FLD automatic display pins P87/SEG; * P-channel open drain output structure * CMOS compatible input level * Please note that this port does not have internal pull- down resistors. P9,/SEG, | I/O port P9 4-bit 1/O port with the same function as port P1 * FLD automatic display pins P9,/SEG,, + P-channel open drain output structure * GMOS compatible input level * This port has internal pull-down resistors. | P9,/SEG,2 | Output port P9 * 4-bit output port with the same function as port PO * FLD automatic display pins P9,/SEGis PApPAz V/O port PA * 8-bit CMOS I/O port with the same function as port P1 : * CMOS compatible input levet * CMOS 3-state output structure PBpy, PB, Input port PB * 2-bit CMOS input port MB 62494828 O02e4038 T60 2392 foursPART NUMBERING MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Product M3818 4 M 8 - XXX FP TT ____________._ RAM size Package type FP : }00P6S-A package FS : 10000 package ROM number Omitted in some types ROM/PROM size 1: 4096 bytes 9 : 36864 bytes 2 : 8192 bytes A: 40960 bytes 3: 12288 bytes B: 45056 bytes 4: 16384 bytes GC: 49152 bytes 5 : 20480 bytes O: 53248 bytes 6 : 24576 bytes E: 57344 bytes 7: 28672 bytes F: 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas; they cannot be used. Memory type M : Mask ROM version E | EPROM or One Time PROM version : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : B96 bytes : 1024 bytes SAN hb wh + Oo MM 6249828 0024039 417? 9 MITSUBISHI - 2+393MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3818 group as foliows: (1) Support for mask ROM, One Time PROM, and EPROM versions . (2) ROM/PROM size rete etna a teas eeeeetesetreeees 32K to 56K bytes RAM size vr -** 640 to 768 bytes (3) Packages 100P6S-A Teeter eee re en eteenasaataenereanens Plastic molded QFP 100D0 Daven e ee ete e cee nen mene senenes Window type ceramic Lcoc Memory Expansion Plan ROM size (bytes) ee 52K Mass product 48K . 44K 40K M38184MA 36K 32K sesseceeeees M38184M8 DBK foesseeeecscecceedenssesenecee 24K 20K soseefecceseseseeceeceduenececeeccnctanapececcssteneeeeefenseteseesesese beeccccenenmeeseecpenneneee TOK, fevenvevesseeeeedeeeeeeeeeeectseebieceeeeee 12K BK [ennessnseeneeeecbeteececceceeeeeebeeeetecssecccsccchananeseerecenecbecnsssanantteeferceceececaastisfecteecscesssessideceee 4K 192 256 384 512 640 768 896 1024 RAM size (bytes) Currently supported products are listed below. As of May 1996 Product {P) ROM size (oytes) } RAM size (bytes) | Package Remarks M38184M8-XXXFP (sees) 640 100pes-a | M@8K ROM version M38184MA-XXXFP 40960 (40830) : Mask ROM version M38185ME-XXXFP Mask ROM version M38185EE-XXXFP 100P6S-A | One time PROM version M38185EEFP 57344 One time PROM version (blank) M38185EEFS (57214) 768 100D0 | EPROM version M38185EEHXXXFP : . One time PROM version 100P6S-A " . M381 85EEHFP One time PROM version (blank) M38185EEHFS 100D0 | EPROM version MH 6249828 OOe4040 435 oe 23m oeMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3818 group uses the standard 740 family instruction - set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User's Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL and DIV instruction can be used. CPU Mode Register The CPU mode register is allocated at address 003B,.. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. b7 bo | ] CPu po mode register (CPUM | address 003B,) LL scone mode bits bibd 0 0 : Single-chip mode o1: 10 : | Not available 11: Stack page selection bit 0 : RAN in the zero page is used as stack area |. RAM in page | is used as stack area Not used (return 0 when read) Xcour drivability selection bit 0 > Low drive 1: High drive Main clock (Xin-Xour) stop bit 0 : Operating 1 | Stopped Internal system clock selection bit 0 : Xin-Xour selected (high-speed operation mode) 1 : Xcw-Xcour selected (low-speed operation mode) Fig. 1 Structure of CPU mode register MM 6249828 0024041 575 PE 2395MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area-in the zero page con- tains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of sub- routine calls and interrupts. , ROM The first 128 bytes and the last 2 bytes of ROM are re- served for device testing and the rest is user area for stor- ing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vec- tors. Zero Page The 256 bytes. from addresses 0000,, to OOFF,, are called the zero page area. The internal RAM and the special func- tion registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Ac- cess to this area with only 2 bytes is possible in the zero page addressing mode. . Special Page The 256 bytes from addresses FF00,, to FFFF,,_ are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 2396 000016 RAM area SFR area RAM capaci 0040 aa pacity Address XXXXj 16 | FLD automatic display RAM area page (bytes) 007016 . 192 OOFF 46 o100 256 013Fy6 RAM |Seriall/Oautomatictransfer RAM area 384 01BF ig 12016 512 023F 16 640 O2BFic 768 033F 16 XXXXig Lowen enon - 896 _ O8BFig 1024 043F ie Reserved area ROM area 44016 ROM capacity | yp adress YYYYie | Address ZZZ7 (bytes) ress 16 ress 416 Not used 4096 F000,6 FO801 WY, Proctcttcccccttc ee 4 8192 E00016 E08016 Reserved ROM 12288 1000,. 08016 area 16384 C0006 C0801. (128 bytes) 20480 B000,. B080,. 2ZZZ16 24576 A00016 A080,, 28672 9000,., 9080,, 32768 8000.6 8080i6 36864 700016 708016 40960 6000.6 6080.6 ROM 45056 500016 "508016 FFODs6 - 49152 4000.6 408016 53248 300016 30801 FFDCig 57344 200016 201016 Special 61440 1000.6 10104, Interrupt vector area page FFFE,, LO FFEF yg Reserved ROM area Fig. 2 Memory map diagram Me 6249828 OOe404e 4Ol MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 0000... | Port PO 000116 0002.5 | Port Pt (Pt 000316 | Port P? direction 0004.5 | Port P2 (P2 0005, P2 direction 000616 P3 (P3 0007.6 0008,. P4 0009,, | Port P4 QO0A;, | Port P5 (P5 0008.6 | Port P5 direction 000C,6 | Port P6 (P6 P6 direction 000Di6 O00E16 OO0F 16 0010,_ | Port Ps 001116 | Port P& 0012,, | Port P9 0013,_ | Port P9 direction 001416 001516 001615 001746 001816 data SIODP. 001916 | Serial 1/01 SIO1CON O01Ai, [ Serial VO 001Bi6 1/01 001C,., automatic transfer 001D,., control OO1E;. OO1F i, Timer 6 (T6 Timer 6 PWM Timer 12 mode Timer 34 mode 56 mode A-D control A-D Port FLDG mode FLD data control Fig. 3 Memory map of special function register (SFR) 0 PORTS Direction Registers The 3818 group has 67 programmable I/O pins arranged in nine I/O ports (ports Pi, P2, P4,-P4,, P5-P8, P9)-P9, and PA ). The I/O ports have direction registers which deter- mine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When 0 is written to the bit corresponding to a pin, that pin becomes an input pin. When 1 is written to that bit, that pln becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin re- mains floating. High-Breakdown-Voltage Output Ports The 3818 group has four ports with high-breakdown-voltage pins (ports PO, P3, P8, P9). The high-breakdown-voltage ports have P-channel open drain output with a breakdown voltage of Vcc 40V. Each pin in Ports PO, P3, and PS has an internal pull-down resistor connected to Veg. Port P8 has no internal pull-down resistors, so that connect an external resistor to each port. At reset, the P-channel output transis- tor of each port latch is turned off, so it becomes Vee level (L) by the pull-down resistor. Writing 1 to bit 0 of the high-breakdown-voltage port con- trol register(address 0038,,) slows the transition of the out- put transistors to reduce transient noise. At reset, bit 0 of the high-breakdown-voltage port control register is set to 0 (strong drive). ME 6249828 0024043 348 we eS 2-397: MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER . - | Diagram Pin Name Input/Output 1/0 Format Non-Port Function Related SFRs : No : FLDC mode register P09/SEG, High-breakdown- a /DIG voltage port control POs/DIGi High-breakdown- 39 Port contro! FLD automatic register voltage P-channel display function FLDC mode register Port PO Output open-drain output play Port PO digit/ 2 igi P0,/SEG,2. with pull-down avP resistor switching register (2) P07/SEGis . High-breakdown- voltage port control register Input/output CMOS compatible P1pP1, Port P1 input/output, input level (3) individual bits CMOS 3-state output P29~P2, Port P2 Input/output, TTL level input (3) individual bits CMOS 3-state output FLDC mod ist High-breakdown- Port Rone 0 eal i nt/digi PS0/SEGi6/ voltage P-channel FLD automatic switchin: ro sister DIGigP37/ Port P3 Output open-drain output display function high emletoun (4) SEGo9/DIG; with pull-down play on voltage port control resistor . register CMOS compatible External interrupt Interrupt ed P4o/INTo Input P P upt ecg (5) input level input selection register P4,/INT, External interrupt Interrupt edge (6) P4,/INT, Port P4 CMOS compatible input selection register Input/ output, . Pas oe . input level (3) individual bits , P46/Tlout, CMOS 3-state output Timer output Timer 12 mode register (7) P47/T30ut P Timer 34 mode register P50/Sin1, Seriat 1/O1 control (8) PS,/ , register Pesan Serial 1/01 function Serial /O automatic | eB Souk CMOS compatible | 1/0 P5a/Srpyv1/ . . transfer control Ges Port PS Input/output, input level register (0) ue individual bits N-channel a P54/Sine, . (8) open-drain output . . . P55/Soure2; Serial 1/02 function | Serial 1/O2 control (9) P5e6/Serk2, vo register P57/Sapy2 40) P6o/PWMo 14-bit PWM output PWM control register ay CMOS compatible * Input/output, . Timer 56 mode register P6,/PWM, Port P6- Purrourp input level 8-bit PWM output mous reg (7) individual bits Timer 6 PWM register CMOS 3-state output P62/CNTRo, Timer 2, Timer 4 input Interrupt edge (6) P6,/CNTR, | , P selection register - P6, P6, (3) , CMOS compatible P7o/ANg input/output, . | . Port P7 ete input level A-D conversion input | A-D control register (12) P77/AN; individual bits CMOS 3-state output. CMOS compatible | P FLDC mode register input level Port P8 segment/port P8/SEG, input/output High-breakdown- | 5 automati itchi veal ti . , . iu Bo Port P8& . Pt . p . voltage P-channel . ale sw ching register (13) P87/SEG? individual bits . display function High-breakdown- open-drain output It ort control without pull-down vo ae, Port contro resistor registor ME 6249828 OoOe4O44 284 me 2398 ooeeMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Diagram Pin Name Input/Output \/O Format Non-Port Function Related SFRs Ne CMOS compatible input level High-breakdown- P9o/SEGg input/output, a. : voltage P-channel (ia) P93/SEGi1 individual bits . open-drain output . FLDC mode register with pull-down . . . FLD automatic High-breakdown- Port P9 resistor display function voltage port trol i High-breakdown- Play ea BP Contra voltage P-channel registor P94/SEGi2 Output open-drain output (15) -draii ut, P9;/SEGi5 P p with pull-down resistor input/output CMOS compatible lu ut, . PAgPA;7 Port PA . , id ie input level (3) individual CMOS 3-state output CMOS compatible PBp, PB, Port PB Input P (8 input level Note 1. For details of how to use double-function ports as function I/O ports, refer to the applicable sections. 2. Make sure that the input level at each pin is either OV or Voc during execution of the STP instruction. When an input level is at an intermediate potential, a currant will flow from Vcc to Vss through the input-stage gate. M 6249828 0024045 110 oe aS 2-398MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports PQo-PO0s Shift signal from previous stage Dimmer signal o (Note) Data bus so Partiatch }, __.4 N Shift signal to next stage (3) Ports P1, P2, P45, P6,4- P67, PA Direction register Port latch Data bus + (5) Port P49 INT, interrupt request (7) Ports P45, P47, P6, Timer 1 output selection bit Timer 3 output selection bit Timer 6 output selection bit P| Direction register bata bus ++ Fora oF | Data bus ________,-o Vee AL b Timer 1 output selection bit _ Timer 3 output selection bit Timer 6 output selection bit * | High-breakdown-voltage P-channel transistor Note. The dimmer signal sets the Tof timing. Fig. 4 Port block diagram (1) (2) Ports PO4-P0,7 Shift signal from previous stage Port PO digit/por! awitching register | Fz | Dimmer signal >o (Note) Data bus +~5~ Port latch Jt A Blanking register Shift signal to next stage (4) Port P3 Shift signal from previous stage Port P3 segment/digit Ot | switching register | ~<] Blanking Dimmer signal>o register ~~ (Note) Data bus Te Port latch * Local data__~ 2 bus 4 . : 2 Shift signal to next stage (6) Ports P4,-P4,, P62, P63 Direction register { rt Data bus Port latch | } INT,-INT, interrupt request GNTRo, CNTR, or timer 4 external clock input (8) Ports P59, P54 register Data bus +4 oh 1 t WT Serial 1/O input ~<q_ MM 62494828 OOe404b OS? me oe ES 2400MITSUBISHI! MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Ports P5,, P52, PSs, P5g (10) Ports P53, PS; Sroy output selection bit Output-off contro! signa! Roy outp Serial (/O port selection bit { Direction L register Direction rO) register C Data bus [Para } | Data bus 4 Port latch ] NI Sour or Setk nepeneneiatetaieatetetey be 5 Srov outputf>} - | Serial clock input : la, 1 Lo -_S J 1 CS input PB2, PSg only L--2-_-S-3 P5, only (1) Port P6, (12) Port P7 PWM output enable bit , Jy register Direction J register Data bus +{Port latch }# = al Data bus -+ = For ateh_}- D> : | A-D conversion input PWM output [> Analog input pin Selection bit (13) Port P8 (14) Ports P99-P93 ane Note) =~ Dimmer sional =o (Note Local data Local data bus * Data bus Port tatch Data bus Port latch * Vee (15) Ports P9,-P9, (16) Port PB Dimmer signal o Data bus} 0 Loca! data (Note) bus y, p * Data bus Batlsch hy A N Vee * : High-breakdown-voltage P-channel transistor Note. The dimmer signal sets the Tog timing. Fig. Port block diagram (2) MM! 6249428 002404? T93 oes 2aMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts occur by eighteen sources: five external, twelve internal, and one software. Interrupt Control Each interrupt is controlled by its interrupt request bit, its interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An in- terrupt occurs if the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is O. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but can- not be set by software. The BRK instruction cannot be. disabled with any flag or bit. The | (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the inter- rupts are received according to priority. Interrupt Operation When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to in- hibit other interrupts from interfering. The corresponding in- terrupt request bit is cleared and the interrupt jump des- tination address is read from the vector table into the prog- tam counter. Notes on Use When the active edge of an external interrupt (INToINT4) is changed or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, plese take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to 0. (4) Enable the external interrupt which is selected. Table 1. Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Request , Interrupt Source Priori rup ty High. Low Generating Conditions Remarks Reset (Note 2) 1 FFFD46 FFFCi6 At reset . Non-maskable At detection of either rising or | External interrupt - INTo 2 FFFBis FFFAts falling edge of INT input (active edge selectable) At detection of either rising or | External interrupt INT, 3 FFF9:6 FFFBi6 falling edge of INT, input (active edge selectable) At detection of either rising or | External interrupt INTa 4 FFF 716 FFF6 16 falting edge of INT2 Input (active edge selectable) | Vatid when serial I/O ordinary Seria Vor ; | oor cera, |i completion of data transfor | mode is selected Serial 1/0 automa- Sis 16 At completion of final data | Valid when serial I/O automa- tic transfer transfer tic transfer mode is selected Serial 1/02 6 FFFS3is FFF2i6 At'completion of data transfer Timer 1 7 FFFi6 FFFOi At timer 1 underflow . Timer 2 8 FFEFi FFEEs At timer 2 underflow STP release timer underflow Timer 3 9 FFEDis FFECi6 At timer 3 underflow Timer 4 10 FFEBic FFEAi. At timer 4 underflow Timer 5 it FFES, FFESi At timer 5 underflow Timer 6 12 FFE7i6 FFE6i At timer 6 underflow : At detection of either rising or | External interrupt INTs 13 FFESi FFE4i falling edge of INT; input (active edge selectable) INT At detection of either rising or | Extemal interrupt valid when INT, inter- 14 EFES FFE2,, _-dalling.edge of INTs input rupt is selected (active edge selectable) 16 18 At completion of A-D conver- | Valid when A-D interrupt is A-D converter sion selected Valid when FLD blanking inter- FLD blanking At falling of final digit 9 o 15 FFEt FFEG. Jo nee reneserrevecseeetae lee selected i . At rising of each digit v when FLD dig FLD digit is selected BRK instruction 16 FFDDi6 FFDCi6 At BRK instruction tion _| No kable software interrupt Note 1. Vector addresses contain interrupt jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. MM 62498628 0024048 I2T 2402 aoeMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit J Interrupt disable tlag(!) q BRK instruction Interrupt request INT, active edge selection bit L____._. INT,/AD conversion | 0 interrupt switching bit po CNTRp active edge selection bit | 0 CNTR, active edge selection bit | 1 7 Interrupt request register 1 . b0 | (IREQ] : address 003C;.) Lo INT, interrupt request bit INT, interrupt request bit INT? interrupt request bit Serial 1/01 interrupt request bit, or Serial |/O automatic transfer interrupt request bit Serial 1/02 interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Lo bd rTLIITLel 4 Interrupt control register 1 (ICON1 : address 003E,) INT, interrupt enabie bit INT, interrupt enable bit INT, interrupt enabie bit Serial 1/01 interrupt enable bit, or Serial 1/O automatic transfer interrupt enable bit Serial 1/02 interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Reset Fig. 6 Interrupt control Sooo Interrupt edge selection register (INTEDGE : address 003A;,) LL INT, active edge selection bit: INT, active edge selection bit 0 : Falling ed tiv ._._- INT, active edge selection bit 1 : Risin as d id ati e INT; active edge selection bit . 9 ecg ve > INT, interrupt : A-D interrupt: : Count at rising edge : Count at falling edge b7 Interrupt request register 2 bd [ (IREQ2 : address 003D,) LL Timer 4 interrupt request bit Timer 5 interrupt request bit _____. Timer 6 interrupt request bit INT, interrupt request bit INT, interrupt request bit, or AD conversion interrupt request bit FLD blanking interrupt request bit, or FLD digit interrupt request bit Not used (return 0 when read) 0 : No interrupt request issued 1 : interrupt request issued b7 Interrupt control register 2 bO CTI l (ICON2 : address 003F,,) L Timer 4 interrupt enable bit Timer 5 interrupt enable bit Timer 6 interrupt enable bit INT, interrupt enable bit INT, interrupt enadie bit, or AD conversion interrupt enable bit FLO blanking interrupt enable bit, or FLD digit interrupt enable bit Not used (returns 0 when read) Not used (returns 0 when read) (Do not write 1 to this bit) 0 : Interrupts disabled 1 interrupts enabled Fig. 7 Structure of interrupt-related registers MM! 6249428 0024049 &bb eeeMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 3818 group has six built-in timers: timer 1, timer 2, tim- er 3, timer 4, timer 5, and timer 6. All timers are count down. When the timer reaches 00,,, at the next count pulse the contents of the corresponding timer latch is loaded into the timer, and sets the corresponding interrupt request bit to 1. Each timer also has a stop bit that stops the count of that timer when it is set to 1. Note that the system clock can be set to either high- speed mode or low-speed mode by the CPU mode reg- ister. Timer 1 and Timer 2. The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. Timer 1 can also output a rectangular waveform from the P46/Tlour pin. The waveform changes polarity each time timer 1 overflows. . The active edge of the external signal CNTR can be set by the interrupt edge selection register. When the chip is reset or the STP instruction is executed, all bits of the timer 12 mode register are cleared, timer 1 is set to FF,,, and timer 2 is set to 01,4,. / Timer 3 and Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. Timer 3 can also output a rectangular waveform from the P47/T3ou7 pin. The waveform changes polarity each time timer 3 overflows. : The active edge of the external signal CNTR, can be set by the interrupt edge selection register. Timer 5 and Timer 6 The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. Timer 6 can also output a rectangular waveform from the P6,/PWM, pin. The waveform changes polarity each time timer 6 overflows. Timer 6 PWM, Mode Timer 6 can also output a rectangular waveform of n cycles high and m cycles low. The n is the value set in timer latch 6 (address 0025,,) and m is the value in the timer 6 PWM register (address 0027,,). If n is O", the PWM, output is L, if m is O and n is not 0, then the PWM, output is H. In PWM mode, interrupts are generated at the rising edge of the PWM, output. Mi 6249428 OO24050 546 mm _ . | MITSUBISHI 2404 ate MISESMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER internal system clock selection bit Timer 1 count Timer 1 latch (8) source 1 selection bit P4e/TTout ai_Timer 1 (8) o Timer 1 count stop bit Data bus RESET < STP instruction Timer 1 interrupt request selection bit P4, direction register Rising/fallin P62/CNTRo CO > edge switch P4;/T3our P4; latch | Timer 3 output selection bit P4, direction register Rising/falling PEYCNTR: OLa> Timer 2 count source selection bit LAL Timer 19" Timer 2 count stop bit oo or, Timer 3 count source selection bit ? Timer 3 - | count stop bit gr 10 Timer 4 count stop bit Timer 2 iatch (8) 218) maa Timer 3 tatch (8) Ltre Timer 2 interrupt request Timer 3 interrupt request Timer 4 interrupt request Timer 6 output selection bit Timer 5 count source 1" (selection bit 2 o" count stop bit Timer 6 count source O1"| selection bit aa oO Timer 6 (8) Timer 6 interrupt r ct 30 PAL_Timer 6 (8) | er 6 interrupt reques L___ 4 =. timers 4 Ll count stop bit Timer 6 PWM register (B) P6,/PWM, P6, latch ee CL AA Timer 6 operating mode selection bit P6, direction register Timer 5 atch (8) Timer 5 (8) timers Lemme Timer 6 latch (8) Timer 5 interrupt request Fig. 8 Timer block dlagram MM 6249828 0024051 414 oe 2405MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 bo rlItrrteet 4 Timer 12 mode register (T12M : address 0028).) Lier 1 count stop bit 0 = Operating 1 : Stopped Timer 2 count stop bit 0 : Operating 1 : Stopped Timer 1 count source selection bit 2 (Xiy)/16 oF (Xo) /16 1 2 1(Xon) Not used (returns 0 when read) Timer 2 count source selection bits bd b4 . 00 : Timer t underflow 01 : (Xen) 10 : External count input CNTRy ~ 11 Not available Timer 1 output selection bit (P4,) 0 : VO port 1: Timer 1 output Not used (returns 0 when read) b7 bd. . [TLC ITT I Timer 56 mode register J (T56M : address 002A,,) Timer 5 count stop bit 0 : Operating 1 : Stopped Timer 6 count stop bit 0 : Operating 1 : Stopped Timer 5 count source selection bit 0 2 (Xiy)/16 OF Xo) /16 1 : Timer 4 underflow Timer 6 operation mode selection bit 0 : Timer mode 1 2 PWM mode : Timer 6 count source selection bits b5 b4 00 2 F(X )/16 oF Xo) /16 0 1 : Timer 5 underflow 10 : Timer 4 underfiow 11 : Not available Timer 6 (PWM,) output selection bit 0 : 1/0 port . 1 Timer 6 output Not used (returns 0 when read) (Do not write 1 to this bit) b7 bo CLITITII TT Timer 34 mode register po 1 address 00291.) Timer 3 count stop bit 0 : Operating 1 : Stopped Timer 4 count stop bit 0 : Operating 1 : Stopped Timer 3 count source selection bit 0 2 #(Xmw)/16 oF f(Xon)/16 1 : Timer 2 undertlow Not used (returns 0 when read) Timer 4 count source selection bits b5 b4 0.0 : (Xn)/16 or (Xe) /16 0 1 : Timer 3 underflow 1.0 : External count input CNTR, 11 : Not available Timer 3 output selection bit (P47) 0 : 1/0 port 1 2 Timer 3 output Not used (returns 0 when read) (P6,) Fig. 9 Structure of timer-related registers Timer 6 count source Timer 6 PWM mode Annu Timer 6 interrupt request Note. If the value set in timer 6 is n and the value set in the timer 6 PWM register is m, a PWM waveform with duty cycle n/(n-+m) and period (n-+m) Xtg is output (where is tg the frequency of the timer 6 count source). Timer 6 interrupt request Fig. 10 Timing in timer 6 PWM, mode Me 6249628 OO24052e 350 ae 2406 oo tsesSERIAL VO The 3818 group has two built-in 8-bit clock synchronized serial |/O channels (seriat 1/01 and serial 1/02). Serial 1/01 has a built-in automatic transfer function.Normal MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial |/O2 can only be used in normal operation mode. serial operation can be set via the serial 1/O automatic transfer control register (address 001Ai). The I/O pins of the serial 1/O function also operate as 1/O port P5, and their operation is selected by the serial I/O control registers (addresses 0019, and 001D,,). Xin PS3/Sapv1 /CS/Serxi2 PS2/Scrnn P,/Sour PSo/Sins P57/Sapva PSe/Scunz P5s/Soure P54/Sinz control register. O O 9 PS, latch > Main Local address bus address bus 1/0 automatic transfer RAM {(0100,, to O17 Fig bus St/O automati 2 Address decoder Internal system clock selection bit (Note) Sao | transfer data pointer 170 automatic transfer controller L-CS P52 latch . g" Othe, Serial 1/01 port selection bit 0 O- PS, latch oe. l erial 1/O counter 1(3 myn : Serial 1/01 port selection bit Oo o P5; latch Serial 1/02 synchronous oO clock selection bit ae Sapy2 Synchronizatl o oe circuit Sapv2 output selection bit Triernal clack Q" x Px latch oy om__ Serial (/O1 register (8) a Serial (/O counter 2(3 Serial 1/02 port selection bit Oo P5, latch qr o Serial 1/02 port selection bit Serial 1/02 register (8) Main data Local data bus Note. Selection is by the synchronization clock selection bit, the Spoy1 output selection bit, and the serial 1/O1 port selection bit of the serial 1/01 Control register, and the automatic transfer control bit and synchronization clock output pin selection bit of the serial |/O automatic transfer Serial 1/0 automatic transfer interrupt request Serial |/O1 interrupt request Serial 1/02 interrupt request Fig. 11 Serial 1/O block diagram M@ 6249628 0024053 297 oe as 2407MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial /O Control Registers (SIO1CON, SIO2ZCON) 0019,,, 001D,, Each of the serial 1/O control registers (addresses 0019,, and 001D,,) contains seven bits that select various control Parameters of the serial 1/O function. b7 bd b7 b0 Serial 1/01 control register (SIO1CON(SC1) : address 001946) Li [ Internal synchronization clock selection bits b2 bt bd 000 ! F(Xin)/8 oF (Xen) /8 + FCKin)/16 of F(Xcuy)/16 0Xin) 432 oF F(Xewn)/32 2 CX) /64 oF f(Xony) 64 5 (Xiw)/128 or 1 Xow) /128 04) /256 or f( Xen) /256 Serial 1/01 port selection bit (P5,, P52, and P53) 0: /O port . 1 Sours Souci, and Scrici2 signal pins Sapyi output selection bit (P53) 0 VO port 1? Srovi/CS* signal pin Transfer direction selection bit 0. : LSB first 1 | MSB first . Serial 1/01 synchronous clock selection bit 0 : External clock 1} Internal clock Not used (returns 0 when read) ~~ OOS 0 1 1 1 1 =-o-0o-8 Serial 1/02 control register (SIO2CON(SC2) : address 001D,) Internal synchronization clock selection bits b2 bl bd 0.00 : (Xsy)/8 or f( Xen) /8 2 O%i/16 or f( Xow) /16 2 (Xin) /32 or (Xen) /32 b> 104i) /64 or f Xen) 464 5 4(Xin)/128 or F(X) /128 2 (Xin)/256 or f( Xein)/256 Serial 1/02 port selection bit (P5; and P5g) 0 : 1/0 port __1_2 Soure and Serke signal pins Sapyv2 output selection bit (P5;) 0 1/0 port 1: Srpvz signal pin Transfer direction selection bit 0 : LSB first 1: MSB first Serial 1/02 synchronous clock selection bit Q : External clock 1: Internal clock Not used (returns 0 when read) 0 0 0 1 1 a ne =-=Oo-0-8 * | Valid only in serial |1/O automatic transfer mode. Fig. 12 Structure of serial 1/O control registers MF 6249828 0024054 123 2-408 PdMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial VO ordinaly Mode Either an internal clock or an external clock can be selected as the synchronous clock for serial I/O transfer. A dedicated divider is built-in as the internal clock, for selecting of six clocks. If internal clock is selected, transfer start is activated by a write signal to a serial 1/O register (address 001By,,5 or O01F,;,). After eight bits have been transferred, the Sguy pin goes to high impedance. lf external clock is selected, the clock must be controlled externally because the contents of the serial 1/O register continue to shift during inputting the transfer clock is. In this case, note that the Sour pin does not go to high impedance state at the completion of data transfer. The interrupt re- quest bit is set at the end of the transfer of eight bits, re- gardiess of whether the internal or external clock is selected. Synchronous clock Transfer clock Serial 1/0 register write signal Serial 1/O output UT Serial \/O input Sin Receive enable signal Srpy after transfer ends. Note. If internal clock is selected, the Sour pin is at high impedance Interrupt request bit set Fig. 13 Serlal I/O timing in normal mode (for LSB first) Serial /O Automatic Transfer Mode The serial 1/01 function has an automatic transfer function. For automatic transfer, switch to the automatic transfer mode by setting the serial 1/O automatic transfer control register (address O01A;,). The following memory spaces are added to the circuits used for the serial 1/01 function in ordinary mode, to en- able automatic transfer mode: * 32 bytes of serial I/O automatic transfer RAM * A serial I/O automatic transfer control register * A serial I/O automatic transfer interval register * A serial (/O automatic transfer data pointer When using serial 1/O automatic transfer, set the serial 1/O control register (address 0019,,) in the same way as for the serial I/O ordinary mode. However, note that when ex- ternal clock is selected and bit 4 (the Srpy: output selec- tion bit) of the serial 1/01 control register is set to 1, port P5, becomes the CS input pin by setting. Serial /O Automatic Transfer Control Register (SIOAC) 001Ai, The serial I/O automatic transfer control register (address 001A;) contains four bits that select various control para~ meters for automatic transfer. b7 bd . (LTTICLIL) Serial 1/0 automatic transfer control register (SIOAC : address 001A4) Automatic transfer control bit 0 : Serial I/O ordinary mode (serial 1/01 interrupt) 1: Automatic transfer mode (serial 1/01 automatic transfer interrupt) Automatic transfer start bit 0 : Transfer completion 1: Transferring(starts of 1 write) Transfer mode switching bit 0 : Fullduplex(transmit and receive) mode 1 Transmit-only mode Synchronous clock output pin selection bit 0 > Seu VS Sounse Not used (return 0 when read) Fig. 14 Structure of serial 1/O automatic transfer control register MM 6249628 0004055 ObT ae MES 2409MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial 0 Automatic Transfer Data Pointer (SIODP) 0018,, The serial 1/O automatic transfer data pointer (address 0018.5) contains five bits that indicate addresses in serial 140 automatic transfer RAM (each address in memory is actually the value in the serial |/O automatic transfer data pointer plus 0100,,). Set the serial 1/O automatic transfer data pointer to (the number of transfer data1), to specify the storage position of the start of data. Serial /O Automatic Transfer RAM The serial 1/O automatic transfer RAM is the 32 bytes from address 01001, to address 011Fi. 011016 O1tEia OF ig Fig. 15 Bit allocation of serial 1/O automatic transfer RAM Setting of Serial /O Automatic Transfer Data When data is stored in the serial 1/O automatic transfer RAM, it is stored with the start of the data at the address set by the serial 1/O automatic transfer data pointer and the end of the data at address 0100,.. Serial /O Automatic Transfer Interval Register (SIOAI) 001C,, The serial I/O automatic transfer interval register (address 001C,.6) consists of a 5-bit counter that determines the transfer interval Ti during automatic transfer. If a value n is written tothe serial |/O automatic transfer in- terval register, a value of Ti= (n+ 2) X Tc is generated, where Tc is the length of one bit of the transfer clock. However, note that this transfer interval setting is only valid when internal clock has been selected as the clock source. Transfer clock Serial 1/0 output Sor 7 DO, 00, X DO, - Serial I/O input YoY on Siw 00, Di, 1 byte data DO; X00, D0, e# ~--- Dis A Die Fig. 16 Serial 1/O automatic transfer interval timing M@ 6249828 O02405b TTh 2410 aEMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Setting of Serial /O Automatic Transfer Timing Use the serial 1/01 control register (address 0019,,) and the serial 1/O automatic transfer interval register (address 001C,) to set the timing of serial 1/O automatic transfer. The serial 1/O1 control register sets the transfer clock speed, and the serial I/O automatic transfer interval regis- ter sets the serial 1/O automatic transfer interval. This setting of transfer interval is valid only when internal clock is selected as the clock source. Start of Serial /(O Automatic Transfer Automatic transfer mode is set by writing 1 to bit 0 of the serial 1/0 automatic transfer control register (address 001Aj), then automatic transfer starts when 1 is written to that bit. Bit 1 of the serial 1/O automatic transfer control register is always 1 during automatic transfer; writing 0 to it is one way to complete automatic transfer. Operation in Serial /O Automatic Transfer Modes There are two modes for serial I/O automatic transfer: full duplex mode and transmit-only mode. Either internal or ex- ternal clock can be selected for each of these modes. Operation in FullDuplex Mode In fuilduplex mode, data can be transmitted and received at the same time. Data in the automatic transfer RAM is sent in sequence and simultaneously receive data is written to the automatic transfer RAM, in accordance with the serial (/O automatic transfer data pointer. The transfer timing of each bit is the same as in ordinary operation mode, and the transfer clock stops at H after eight transfer clocks are counted. [f internal clock is selected, the transfer clock remains at H for the time set by the serial 1/O automatic transfer interval register, then the data at the next address indicated by the serial I/O automatic transfer data pointer is transferred. If external clock is selected, the setting of the automatic transfer inter- val register is invalid, so the user must ensure that the transfer clock is controlled externally. Data transfer ends when the contents of the serial !/O auto- matic transfer pointer reach 00,,". At that point, the serial 1/0 automatic transfer interrupt request bit is set to 1" and bit 1 of the serial 1/O automatic transfer control register is cleared to 0 to complete the serial 1/O automatic transfer. Operation in Transmit-Only Mode The operation in transmit-only mode is the same as that in full duplex mode, except that data is not transferred from the serial 1/01 register to the serial I/O automatic transfer RAM. Transfer direction selection bit Sin Transfer clock LSB first (SC1s=0) : MSB uss MSB first (SC1.=1) : LSB MSB DO; | DOg | DOs | 00, | DO | DO2 | DO, | 004 Sour Dlp | OO; | DO, | DOs | DO, | DO; | DO, | DO, | > Di, | Dip | OO; | DOg | DO; | DO, | DOs | DOZ] > Diz | Di; | Dlg | DO, | DOg| DOs | DO, | DO, > Diy | Dig | Dis | Dlg | Dig | Oly | Dh | Oly Serial 1/01 register Fig. 17 Serial 1/01 register in fullduplex mode ME 6249828 0024057 93 Peet 2-411MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER If Internal Clock is Selected _ If internal clock is selected, the P53/Spapyi/CS/Scuxi2 pin can be used as the Sapy, pin by setting the SC1, bit to 1. If internal clock is selected, the P53 pin can be used as the synchronization clock output pin Scixi2 by setting the SIOAC; bit to 1. In this case, the Soik, pin is at high im- pedance. Select the function of the P53/Srpyi/CS/Soiqi2 and P5,/ Seiki pins by setting bit 3 (SC13), bit 4 (SC1,), and bit 6 (SC1g) of the serial 1/01 control register (address 00194.) ~ and bit 3 (SIOAC3) of the serial 1/O automatic transfer con- trol register (address 001A,,). (Refer to Table 2.) If using the Seiki and Sorxie pins for switching, set the P5a/Srpvi/CS/Serki2 pin to PS; by setting the SC1, bit to 0, and set the P5, direction register to input mode. , Make sure that the SIOAC, bit is switched after automatic transfer is completed, while the transfer clock is still H. Table 2. Seiki and Soixi2 selection SCte SC14 SC3, SIOAC, | P52/Sciki | PSs/Souxse 0 Sours P5g 1 0 1 High 1 . Scricaa impedanse Note. SC1, : Serial 1/01 port selection bit SC1, : Sroy: output selection bit SC1, : Synchronization clock selection bit SIOAC3 : Synchronization clock output pin selection bit Bit 1 write signal of serial 1/O automatic transfer f___ _- control register Serial 1/0 -- control register bit + l LU Write signal from RAM to - fl fli. ! serial 1/01 register vl Write signal.from serial 1/01 | JU -- register to RAM iy | Data pointer nl (K __. al 8 i T T T Transfer clock = LPL (internal or Scuic output) Receive 4 enabled signal. LJ Sroy Serial 1/0 output - - ~-{50.X 00; X00; KBO;XO;XD0; OO X00;}- KEK] PY00.X00,)- = === Sour Serial VO ings (EXE EEX ELEM EEX EE -- XPEXT KNEE Transfer interval Fig. 18 Timing during serial 1/O automatic transfer (Internal clock selected, Sapy used) Bit 1 write signal af serial 1/O automatic transfer N control register Serial 1/O automatic transfer j control register bit 1 . Write signal from RAM to - ry JL. serial 1/01 register Write signal from serial 1/01 register to RAM : Data pointer m SIOAC, - r o Transfer clock i (internal) LLU t Scux output |_ PLLA =F = Scrxi2 output Serial t/O output Serial 1/O input z Sin: CXENKE EXE KEN XE 2 Sour ~~ XO NEE NEO NOT KOO NOGNOGI- -- KENT 05)- OLX XE K Or fen jl anne Wounr = = ~00,K00,X00,X do. Ot 1X Ot. F Dis Transfer interval Fig. 19 Timing during serial 1/O automatic transfer (internal clock selected, Scixi1 and Scoiki2 used) M! 6249828 0024058 675 2412 oesMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER If External Clock is Selected lf an external clock.is selected, the internal clock and the transfer interval set by the serial 1/O automatic transfer in- terval register are invalid, but the serial [/O output pin Soyy and the internal transfer clock can be controlled from the outside by setting the Sgoy; and CS (input) pins. When the CS input is L, the Sour pin and the internal transfer clock are enabled. When the CS input is H, the Sour pin is at high impedance and the internal transfer clock is at H. Select the function of the P5s/Sroyi/CS/Scikiz pin by set- ting bit 4 (SC14) and bit 6 (SC1,) of the serial 1/01 control register (address 0019,) and bit 0 (SIOAC,) of the serial I/O automatic transfer control register (address 001Aj,). Make sure that the CS pin switches from L to H or from H to L while the transfer clock (Scix input) is H after one byte of data has been transferred. lf external clock is selected, make sure that the external clock goes L" after at least 9 cycles of the internal system clock after the start bit is set. Leave at least 11 cycles of the system clock free for the transfer interval after one byte of data has been transferred. if CS input is not being used, note that the Sour pin will not go high impedance, even after transfer is completed. It CS input is not being used, or if CS is L, control the ex- ternal clock because the data in the serial I/O register will continue to shift while the external clock is input, even after the completion of automatic transter. (Note that the automa- tic transfer interrupt request bit is set and bit 1 of the auto- matic transfer register is cleared at the point at which the specified number of bytes of data have been transferred.) Table 3. P5s/Srpy:/CS selection SCts SCI, SIOAG 0 x 0 0 1 1 Note. SC1,: Srpy, output selection bit SC1 : Synchronization clock selection bit SIOAC, : Automatic transfer control bit Bit 1 write signal of serial [/O automatic transfer control register Serial |/O automatic transfer control register bit 1 Write signal from RAM to serial 1/01 register ht fl Write signal from serial 1/01 register to RAM Data pointer n External input cs | Serial I/O output Sour ~ . : \ Serial v0 ingat ROUX ON ADIEKDRKOUXDIXOIXDL XK XK XX KX XXX I Transfer clock Serk input | { | | Tartana) UU (internal) | | | | TTT ae Note. Data marked with X is invalid. Fig. 20 Timing during serial I/O automatic transfer (external clock selected) MB 6249628 0024059 705 PER 2-413MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) OUTPUT CIRCUIT The 3818 group has a PWM function with a 14-bit resolu- tion. When the oscillation frequency Xj, is 8MHz, the mini- mum resolution bit width is 250ns and the cycle period is 4096s. The PWM timing generator supplies a PWM con- trol signal based on a signal that is half the frequency of the Xi clock. _ The explanation in the rest of this data sheet assumes (X ny) =8MHz. Data bus ( Set ta 1 at write PWML register(address 002D1.) i] 7] | i | | | | bitd| PWMH register (address 002C,) 9 = PWM latch(14bits) lwse] | [-se t 7 When setting 0 to internal P6> latch clock selection bit P6)/PWM PWM Xow o~ 14-bit PWM circuit o x ' o PWM output iN O- a9" t selection bit PWM output PWM (648 period) selection bit V2 timing P65 direction generator |(4096us period) register Fig. 21 PWM block diagram Mi 6249428 0024060 427 2-414 eSMITSUBISHI] MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data Set-up The PWM output pin also functions as port P6. Set port P65 to be the PWM output pin by setting bit 0 of the PWM mode register (address 002B,,). The high-order eight bits of output data are set in the high-order PWM register PWMH (address 002C,,) and the low-order six bits are set in the low-order PWM register PWML (address 002D,.). Transfer From Register to Latch Data written to the PWML register is transferred to the PWM latch once in each PWM period (every 4096s), and data written to the PWMH register is transferred to the PWM latch once in each sub-period (every 64us). When the PWML register is read, the contents of the latch are read. However, bit 7 of the PWML register indicates whether the transfer to the PWM latch is completed; the transfer is completed when bit 7 is QO. Table 4. Relationship between lower 6 bits of data and period set by the ADD bit PWM Operation The timing of the 14-bit PWM function is shown in Fig. 24. The 14-bit PWM data is divided into the low-order six bits and the high-order eight bits in the PWM latch. The upper eight bits of data determine how long an H"- level signal is output during each sub-period. There are 64 sub-periods in each period, and each sub-period is 256 X T (64s) long. The signal is H for a length equal to N times T, where T is the minimum resolution (250ns). The contents of the low-order six bits of data enable the lengthening of the high signal by tT (250ns). As shown in Fig. 21, the six bits of PWML determine which sub-cycles are lengthened. As shown in Fig. 24, the leading edge of the pulse is leng- thened. By changing the length of specific sub-periods in- stead of simply changing the H duration, an accurate waveform can be duplicated without the use of complex ex- ternal filters. Lower 6 Bi | = . . . . . sal ee 0 nN = Periods tm Lenothened (m =0 to 63) For example, if the high-order eight bits of the 14-bit data on + ; S ; , 1 | m=32 4 are 03, and the low-order six bits are 0545, the length of 000010 | m=16,48 the H-level output in sub-periods tg, tog, tga, tag, AN tg is 4 000100 | m=8,24,40,56 T, and its length 37 in all other sub-periods. 001000 | m=4,12,20,28, 36, 44,52, 60 010000 m= 2, 6,10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 100000 m=1,3,5,7,--~ , 57, 59, 61,63 4096 ns 64us \ 64us 64us G4us 64us m=0 m=7 m=8 m=9 m=63 15. 754s 18. 75us 15. us bus 15. 75us 15. 754s 15. 75us Pulse width modulation register H : Oo11i111 Pulse width modulation register L : 000101 Sub-periods where H pulse width is 16s : m=8, 24, 32, 40, 56 Sub-periods where H pulse width is 15. 75s : m=ail other values Fig. 22 PWM timing - M@ 6249828 0024061 3b3 MITSUBISHI 2-415MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 bo PWM mode register (address 0028,.) L PGo/PWM output selection bit 0 : 1/0 port 1 > PWM output Not used (return 0 when read) Fig. 23 Structure of PWM mode register Data 6GAj, stored at address 002C,, Data 7B, stored at address 002Ci Example 2 6A ' PWM output | Low-order 6-bit output - H=6Aj,, L=18;5 == Minimum bit width tr =0. us PWMH register 5916 | BAe | N 7Bre Data 241, stored| at address 002Di Bit 7 cleared after transfer Data 36,, stored at address 002D1, PWML ~ 7 register 1316 | Ate 8 2416 | 3 386 | Transfer from register to latch BSi A | Transfer from register to latch PWM latch WM late [16536 | 1093.6 TAA4 6 ee Se Y 1EFSi / =4096u8 When bit 7 of PWML is 0, transfer from register to latch is disabled. ~ (64X64x8) oo . ee. ao - To - _ t=64us - Example! 6A |6B 6A 68 6A 6B 6A 6B 6A 6B [6B |6B GA 6B 6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6A PWM output Low-order 6-bit output : 7 . | 5 51245 5 5 5 5 H=6Ajg, L= 241g 5 5 5 ' 6Big------- 36times Aig ++ 2Btimes___ a 19664-4436 (107) (106) 6A 6A 6A 6B 6A 6B 6A 68 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A ~ se t=64us (256X0. 25s) 106 X64-+24 6A 6B 6A 6B 6A 6B _sl PWM output Fea} GA; 69 $68 1 674 @ ADD ADD 8-bit 102 401} 00] FF }FEs FOS FCI --- 197 $96 95 $02$ 014 00 FFF {FES FDSFCS ~~~ 197 196 $95 8 counter The ADD A Portions with additlonal t are H period length specified by PWMH determined by PWML. 2567 (64us), fixed Fig. 24 14-bit PWM timing M@ 6249428 O0cCk0 2416 be cTT 7 PateMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The functional blocks of the A-D converter are described below. A-D Conversion Register (AD) 0031,, The A-D conversion register is a read-only register that contains the result of an A-D conversion. This register should not be read during an A-D conversion. A-D Control Register (ADCON) 0030,, The A-D contro! register controls the A-D conversion pro- cess. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at 0 during an A-D conversion, then changes to 1 when the A-D conversion is completed. Writing O to this bit starts the A-D conversion. Comparison Voltage Generator The comparison voltage generator divides the voltage be- tween AVss and Vrer by 256, and outputs the divided vol- tages. Channel Selector The channel selector selects one of the input ports P77/AN7 to P7o/ANo. Comparator and Control Circuit The comparator and control circuit compares an analog in- put voltage with the comparison voltage and stores the re- sult in the A-D conversion register. When an A-D conver- sion is completed, the control circuit sets the AD conver- sion completion bit and the AD interrupt request bit to 1. Note that the comparator is constructed linked to a capaci- tor, so set f (Xy) to at least 500kHz during A-D conversion. b7 A-D control register (AOCON : address 0030,) Analog input pin selection bits b2 bl bd 00 : P?7o/ANg 01 P7,/AN, 10 > P72/ANg 11 2 P73/ANg 00 : P74/AN, 01 > P76/ANs 10 : P76/ANG 11: P?;/AN; AD conversion completion bit 0 : Conversion in progress 1: Conversion completed Not used (return 0 when read) ____-__.____ Not used (return 0 when read) (Do not write 1 to these bits) 0 0 0 0 | 1 1 1 Fig. 25 Structure of A-D control register Oata bus A-D control register P7o/ANo P7,/AN, P72/AN2 P73/AN3 P74/ANg P?75/AN5 P76/ANg P7;,/AN7 Comparator Channel selector A-D control circuit A-D interrupt request conversion 8 _ Resistor ladder Veer AVss Fig. 26 A-D converter block diagram MH 6249428 0024063 136 ae 2-417FLD CONTROLLER The 3818 group has fluorescent display (FLD) drive and control circuits. The FLD controller consists of the following components: 24 pins for segments * 16 pins for digits MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER * Port PO digit/port switching register * Port P8 segment/port switching register Key-scan blanking register * 48-byte FLD automatic display RAM Eight to twenty-four pins can be used as segment pins and four to sixteen pins can be used as digit pins. Note that only 32 pins (maximum) can be used as segment. * FLDC mode register * FLO data pointer FLD data pointer reload register * Port P3 segment/digit switching register and digit pins. In the FLD automatic display mode ports P1, to P13 function as digit pins DIG, to DIG,, automatically. bus bus Main address FLD automatic RAM 0040, 004F. Local address FLD data pointer reload register(address 003715) Address decoder (address 0037 Timing generator Main data Local data bus bus Key-scan blanking register (address 003316 FLD blanking interrupt FLD digit interrupt Fig. 27 FLD control circuit block diagram MH 6249428 OO240b4 O72 2418 eseMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLDC Mode Register (FLDM) 0036,, .Key-scan Blanking Register (KSCN) 0035,, The FLDC mode register (address 0036,,) is a seven bit The key-scan blanking register (address 0035;,) is a two control register which is used to control the FLD automatic bit register which sets the blanking period Tscan between display. the last digit and the first digit of the next cycle. b?7 bd | | FLOC mode register(FLDM : address 00361.) Automatic display control bit(PO, P3, P8, P9) 0 : Normal mode 1; Automatic display mode Display start bit 0 : Display stopped 1 : Display in progress (display starts when 1 is written to this bit) Tdisp control bits (digit timing setting, when operating at 8MHz) b b3 b2 :64us 112Bus + 192us + 256us : 3208 : 384us : 448us 1 5l2us trol bits (digit/segment-off timing setting) O-o-0o-0 ee el To 1/16XT disp 1: 10/16XTgisp 10 | 12/18XTdisp 11 5 14/16XTdisp Not used (returns 0 when read) oo Fig. 28 Structure of FLDC mode register (FLDM) b7 bo J Key-scan blanking register(KSCN : address 0035.) Tscan control bits ot bd 0 0 | FLD digit interrupt(at rise of each digit) 01 1XTgisp FLD blanking i 10 :2XTgis inking interrupt 11 2 3XTaisp (at fall of final digit) Not used (returns 0 when read) Fig. 29 Structure of key-scan blanking register (KSCN) ~ mg 6249828 COevOLS TOS eee aaMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLD Automatic Display Pins the FLDC mode register (address 0036,) to 1. The FLD automatic display function of Ports P3, PO, P9, and When using the FLD automatic display mode, set the num- P8 is selected by setting the automatic display control bit of ber of segments and digits for each port. Table 5. Pins in FLD automatic display mode Port Name Automatic Display Pins , Settlng Method SEGo-SEG, The individual bits of the Port P&8 segment/port switching register (address 0034,,) can be used to set each P8o-P87 om pin to either segment (1) or normal port input (0). . P8-P87 P9_-P97 SEG,-SEGis None (segment only) SEGie-SEG2a , . . P3o-P3> The individual bits of the Port P3 segment/digit switching register (address 0032,,) can be used to set each or? o pin to segment (1) or digit (0). (Note) : DiGo-DIG7 . P0)-P03 DIGs-DIGy, None (digit only, use all bits always) DiGi2-DiGis P0,-PO The individual bits of the Port PO digit/port switching register (address 0033;,) can be used to set each pin wer oo to digit (1) or normal port output (0). (Note) POQ,-P0; Note. Always set digits in sequence. Number of segments 8 16 Number of digits 12 10 Port P8 (has Port P8 segment/ port switching register) 0 0 0 0 0 0 0 0 0 1 0 1 Q 1 0 1 Q[Ormo So rolol/o|/o Port P9 (segment only) 0 | DIG +G12 1 0 | DIG, +G16 0| DIG, ~@11 1 0| DIG, G15 0 | DIG, +G10 1 0| DIG, G14 (has port F3 segment/ 0 | DIG, ~G9 1 0 | DIG, G13 digit switching register) 0 | DIG, ~GB 0 O| OIG, +612 0 | DiGs G7 0 0 | DIGs +G11 0 | DIG, ~G6 0 0 | DIGs +G10 0; DIG; ~G5 0 0 | DIG; >G9 DIG, +G8 DIG, ~G8 ; DIG, --G7 DiGy G7 Port PO DIGyo ~G6 DIGig + G6 (has Port PO digit/port DIG), ~G5 DIG,, +G5 switching register) 1] DIGy. ~G4 1| DIG, G4 1 | DiGi +G3 1 | O1Gy, G3 1 | DIGy4 +G2 1 | DIG,, +G2 LI | DIG, ~G1 1} DIG,, +G1 Fig. 30 Segment/digit setting example ; ME 6249828 OO240bb 4S me rt oanMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLD Automatic Display RAM The FLD automatic display RAM area is the 48 bytes from addresses 0040,, to O06F,.. The FLD automatic display RAM area can be used to store 3-byte data items for a maximum of 16 digits. Addresses 0040. to 004F,, are used for P8 segment data, addresses 0050,, to 005Fig are used for P9 segment data, and addresses 0060,, to O06F,, are used for P3 segment data. FLD Data Pointer and FLD Data Pointer Reload Register The FLD data pointer indicates the data address in the FLD automatic display RAM to be transferred to a segment, and the FLD data pointer reload register indicates the address of the first digit of segment P3. Both the FLD data pointer and the FLD data pointer reload register are allocated to address 0037,, and are 6-bits wide. Data written to this address is written to the FLD data pointer reload register, data read from this address is read from the FLD data pointer. The actual memory address is the value of the data pointer plus 40,6, 5045, or 6046. The contents of the FLD data pointer indicate the first address of segment P3 (the content of the FLD data poin- ter reload register) at the start of automatic display. The content of the FLD data pointer changes repeatedly as fol- lows: when transferring the segment P3 data to the seg- ment, the content decreases by16; when transferring the segment P9 data to the segment, it decreases by 16; when transferring the segment P8 data to the segment, it increases by +31. After it reaches 00,,, the value in the FLO data pointer reload register is transferred to the FLD data pointer. In this way, three bytes of data for the P3, P9, and P8 segments of one digit are transferred. Address 0041 Final digit (final data of _ segment P8) Segment P8 data area Final digit (final data of segment P9) Segment P9 data area Final digit ~- (final data of segment P3) Segment P3 data area Fig. 31 FLD automatic display RAM and bit allocation ~ MM 6249428 0024067 541 Mm Pe 2421MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data Setup When data is stored in the FLD automatic display. RAM, the end of segment P8 data is stored at address 0040j, the end of segment P9 data is stored at address 00504, and the end of segment P3 data is stored at address 0060,,. The head of each of the segment P8, P9, and P3 data is stored at an address that is the number of digits1 away from the corresponding address 0040,, 005016, 00601.. Set the value (the number of digits 1) to the low-order four bits of the FLD data pointer reload register. 1 is al-. ways written to bit 5, and 0 is always written to bit 4. Note that 0 is always read from bit 5 or 4 during a read. For 17 segments and 15 digits (FLD data pointer reload register=14) Bit 7 6 5 4 Note. Shaded areas are not used. For 24 segments and 8 digits (FLD data pointer reload register=7) Bit 7 6 4 Fig. 32 Example of using the FLD automatic display RAM. MB 6249624 OOL240bS 718 2422 AMESMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Setting The digit timing (Tdisp) and digit/segment turn-off timing (Toft) can be set by the FLDC mode register (address 0036,). The scan timing (Tscan) can be set by the key- scan blanking register (address 0035,.). Note that flickering will occur if the repetition frequency (1/ (Taisp X number of digits+Tscan)) is an integral multiple of the digit timing Taisp. FLO Start To perform FLD automatic display, you have to use the fol- lowing registers. * Port P3 segment/digit switching register Port PO digit/port switching register * Port P8 segment/port switching register * Key-scan blanking register * FLD data pointer * FLDC mode register Automatic display mode is activated by writing 1 to bit 0 of the FLDC mode register (address 00361.) and the auto- matic display is started by writing 1 to bit 1. During automatic display bit 1 always keeps 1, automatic display can be interrupted by writing O to bit 1. If key-scan is to be performed by segment during the key- scan blanking period Tscan, 1. Write 0 to bit 0 (automatic display control bit) of FLDC mode register (address 0036,,). 2. Set the port corresponding to the segment to the normal port. 3. After the key-scan is performed, write 1 (automatic dis- play mode) to bit 0 of FLDC mode register (address 0036,.). Note on performance of key-scan in the above 1 to 3 order. 1. Do not write 0 to bit 1 of FLDC mode register (address 00364). 2. Do not write 1 to the port corresponding to the digit. FLD digit interrupt generated at the rising edge of segment data Tdisp Tscan Go J 1 Go-l J L J L Gn-2 { 1 J ] G1 Segment ChuCNO0O a am Gan aan) Gas output We Segment setting by software FLD blanking interrupt generated at the falling of edge of the last digit Digit me fF Toft Tdisp Fig. 33 FLDC timing MM 6249428 0024069 654 ELECTRIC 2-423MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT After a reset, the microcomputer will start in high-speed op- eration start mode or low-speed operation start mode depend- ing on a mask-programmable option. High-Speed Operation Start Mode In high-speed operation start mode, to reset the micro- computer occurs, the RESET pin is held at an L level for 2u8 or more. Then is returned to an H level (the power source voltage should be between 4.0V and 5.5V), reset is released. Both the Xi, and the Xin clocks begin oscillating. In order to give the Xj clock time to stabilize, internal op- eration begins until after 13 X~ clock cycles are com- pleted. After the reset is completed, the program starts from the address contained in address FFFD,, (high-order byte) and address FFFC,. (low-order byte). "4 Poweron Power source, 1 (Note) RESET Veo | voltage =H | ov | 36 91 tA | > Reset input | = voltage Note. Reset release voltages - In high-speed operation start mode Voc=4. 0V In low-speed operation start mode } Voo=2. 8V Power source voitage ae detection circuit I | } | | l Fig. 34 Poweron reset circuit example Low-Speed Operation Start Mode In low-speed operation start mode, to reset the microcompu- ter occurs, the RESET pin is held at an L" level for 2s or more. Then is retumed to an H level (the power source vol- tage should be between 2.8V and 5.5V). The Xi clock does not begin oscillating. In order to give the Xen time to stabilize, timer 1 and timer 2 are connected together and 512 cycles of the Xow/16 are counted before internal operation begins. After the reset is completed, the program starts from the address contained in address FFFDj, (high- order byte) and address FFFC;, (low-order byte). If the Xcin clock is stable, reset will complete after approx- imately 250ms (assuming f(Xoyy) =32.768kKHz). Immediately after a poweron, the stability of the clock cir- cuit will determine the reset timing and will vary according to the characteristics of the oscillation circuit used. Note on Use Make sure that the reset input voltage is less than 0.8V in high-speed operation start mode, or less than 0.5V in low- speed operation start mode. MH 62494625 OOevx070 376 2-424 are 7MITSUBISH! MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address - Register contents Address Register contents (1) Port PO register (000 04,6) G1) Timer 12 mode register (002 Big) 8 (2) Port P1 register (000 246) G2) Timer 34 mode register (00 2 949) 8 2 2S oa (3) Port P1 direction register (000 346) G3) Timer 56 mode register (00 2 Aj): (4) Port P2 register (000 445) 0015 @4) PWM control register (0 0 2 By): (5) Port P2 direction register (00 0 546): 8 G5) A-D control register (0.0 3 O49) 0816 (6) Port P3 register (00 D 6 yg) 00,6 G6) Port P3 segment/digit (0.03 246)--- 0016 (7) Port P4 register (000 84g) switching register (8} Port P4 direction register (00 0 Gig) 00,6 (37) Port PO digit/port switching register (0 0 3 346) 0016 (9) Port P5 register (000 Aig) G8) Port PB segment/port (003 446) (1) Port P5 direction register = (0 0 0 Big): switching register (1) Port P6 register (00 0 C4) a (9) _Key-scan blanking register (0 0 3 54)** - | 42 Port P6 direction register (0 0 0 Dig): (0) FLDC mode register (003 6 ye) (13) Port P7 register (00 0 E45): 1) High-breakdown-voltage port = (0 0 3 846) (1) Port P7 direction register = (0 0 0 F 4g) control register (13). Port P8 register (0.01 04) 16 42) Interrupt edge selection register (0 0 3 Aig)-* 0046 (18) Port P8 direction register (001 146) 0015 43) CPU mode register (00 3 Big): |*|1/o[o]o]o| (17) Port P9 register (001 246)" (4) Interrupt request register 1 (0 0 3 C4)" (18) Port P98 direction register (001 346)" F016 @) interrupt request register 2 (0 0 3 Dig)-- a (1) Port PA register (0.01 446)--- 48) Interrupt control register 1 (0 0 3 Eig): (Qt) Port PA direction register (00 1 546): (47) interrupt control register 2. (0 0 3 F yg) Or] gis siigis| |g rs @1 Serial 1/01 control register (001 949): a = cI Processor status register (PS) x]xPxbe]s xx (P C_)-+ [Contents of address FFFCj5 02) Serial 1/O automatic transfer (0 0 1 Ayg}- 4) Program counter (PCy) control register 3 a 3 2 zs 2 & a S 8 a n n ua 2 (23) Serial 1/0 automatic transfer (0 0 1 C4)-* interval register @4) Serial 1/02 control register (0 0 3 Dye): 25) Timer 1 register (0 0 2 046)-- @6) Timer 2 register (00 2 Vig @7) Timer 3 register (00 2 24,)--- FFig 8) Timer 4 register (00 2 346)-- @9 Timer 5 register (00 2 4,4) G0) Timer 6 register (0.02 546) FFis Note. #* : The initial values of bits 7 and 6 of the CPU mode register are determined by a mask option. X : Undertined The contents of alt other registers and RAM are undefined after a reset, so programs must set their initiat values. Fig. 35 Internal status at reset MB 6249628 0024071 20c MITSUBISHI ate MISES 242sMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Xour (8. 4MHz) | Time necessary for oscillation to stabilize i Time until oscillation starts Xcour ' (32kHz) St : oy XN a Time until oscillation starts . i ~ Internal . : reset 0. 24u8 Address | | X XX. YerecXrrroYan..X SYNC . . __T LL Fig. 36 Reset sequence in high-speed operation mode Data 5.5V Vee 9 py ( | He acer | Ke a (Oscillation stopped) Xour . (8. 4MHz) ~ Xeour (32kHz) Time until oscillation starts | Time necessary for oscillation to stabilize = internal reset 62. 54s clock ; Address x X YX XerrecX reo Xap, .X Data ADL ( ADn ) Fig. 37 Reset sequence in low-speed operation mode. MB 6249828 0024072 145 _ MITSUBISHI 2426 ate MISESMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT To supply a clock signal, input it to the Xin (Xo) pin and make the Xour (Xcour) pin open. If the Xow clock is not used, connect the Xow pin to Vgs, and leave the Xcour pin open. Either high-speed operation start mode or low-speed op- eration start mode can be selected by using a mask option. High-Speed Operation Start Mode After reset has completed, the internal clock is half the frequency of X\y. Immediately after poweron, both the Xin and Xcin clock start oscillating. To set the internal clock to low-speed operation mode, set bit 7 of the CPU made register (address 003B,,) to 1. Low-Speed Operation Start Mode After reset has completed, the internal clock is half the frequency of Xcww. Immediately after poweron, only the Xcin clock starts oscillating. To set the internal clock to high- speed operation mode, first set bit 6 (CM,) of the CPU mode register (address 003B,,) to 0, the set bit 7 (CM) to 0. Note that the program must allow time for oscillation to stabilize. Oscillation Control Stop Mode If the STP instruction is executed, the internal clock stops at an H level. Timer 1 is set to FF,, and timer 2 is set to Ot16". Either Xiy or Xcin divided by 16 is input to timer 1, and the output of timer 1 is connected to timer 2. The timer 1 and timer 2 interrupt enable bits must be set to disabled (0), SO a program must set these bits before executing an STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait Mode If the WIT instruction is executed, the internal clock stops at an H level but the oscillator itself does not stop. The in- ternal clock restarts if a reset occurs or when an interrupt is . received. Since the oscillator does not stop, norma! opera- tion can be started immediately after the clock is restarted. Low-Speed Mode If the internal clock is generated from the sub-clock (Xcin), a low power consumption operation can be entered by stopping only the main clock Xin. To stop the main clock, set bit 6 (CMg) of the CPU mode register (003B,,) to 1. When the main clock X is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the Xcin-Xcour drivability can be reduced, allowing even lower power con- sumption (204A with f (Xcn) = 32kHz). To reduce the Xcin-Xcour drivability, clear bit 5 (CMs) of the CPU mode register (003B,) to 0. At reset or when an STP instruc- tion is executed, this bit is set to 1 and strong drivability is selected to help the oscillation to start. Xcin Xcour Xin Xout 36 7 38 39 7 ae Ceour 7 Cw ao Fig. 38 Ceramic resonator circult Xorn Xcour Xin Xour 36 37 39 3 - Open Open External oscillation circuit or pulse External oscillation circuit * Veco | j | j ve JULY Vss Vss Fig. 39 External clock input circuit MB 6249828 0024073 085 eee 2427MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Xen . * Xgour Timer 1 count stop bit Timer 2 count stop bit Xin : Xour OD 9 Timer | count source selection bit Internal system clock selection bit CM; (Note) Timing (Internal clock) Main clock stop bit CMe internal system clock selection bit CM; cor | POSE ke Reset WIT R RE- STP instruction instruction Ri- stp instruction Reset Interrupt disable flag | interrupt request Note. The values of CM; and CMg at reset are determined by a mask option. Fig. 40 System clock generation circuit block diagram MB 6249828 Goe4074 TLL MITSUBISHI 2428 . . PRSMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER High-speed operation start mode(Note 4) WIT STP . instruction alee: instructi Xin clock oscillating 2 Xin Clock oscillating TU Xn clock stopped Xein clock oscillating Xcin Glock oscillating Xen Clack stopped is stopped (H") __ O=1(Xiy) /2 < # is stopped (H) Timer operating Interrupt Interrupt (Note 1) External interrupt, External interrupt, or timer interrupt, or CM;=0 Serial 1/O interrupt Serial I/O interrupt CM;= WIT STP %w Clock oscillating instruction ; instruction Xcww clock oscillating <__. Xin clock oscillating se %w clock stopped ; ope Xein Clock oscillating Xcin Clock stopped is stopped (H) > CIN < on Opp: Timer operating $= 1( Xow) /2 is stopped (H") (Note 3) Interrupt Interrupt (Note 2) CM,=0 The program must CM.=1 allow time for Xin oscillation to stabilize Wit STP Xn clock stopped instruction instruction Xein Clock oscillating <_ Xn clock stopped Xw clock stopped ; apy Xoin clock oscillatin X lock d is stopped (H") CIN 9 cin Clock stoppe Timer operating b= f( Xen) /2 =stopped (H) (Note 3) Interrupt Interrupt (Note 2) Low-speed operation start mode (Note 4) The example assumes that 6. 3MHz is being applied to the Xiy pin and 32kHz to the Xow pin. Note 1. When the STP state is ended, a delay of approximately 1. 3ms is automatically generated by timer 1 and timer 2. 2. The delay after the STP state ends is approximately 0. 25s. 3. if the internal clock divided by 8 is used as the timer count source, the frequency of the count source is f(Xoi)/16. 4. Specify this option when ordering a mask ROM version. Fig. 41 State transitions of system clock MM! 6249626 0024075 156 MITSUBISHI 2429WM 6249828 0024076 394 mm MITSUBISHI] MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (1) which is 1". After a reset intialize flags which affect prog- ram execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags be- cause of their effect on calculations. interrupts The contents of the interrupt request bits do not change im- mediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS in- struction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to 1, then execute a ADC. or SBC instruction. Only the . ADC and SBC instruction yleld proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruc- tion. : In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n-+1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used : * the data transfer instruction (LDA, etc.) * the operation instruction when the index X mode flag (T) is 1 , mo * the addressing mode which uses the value of a direction register as an index. . * the bit-test instruction (BBC or BBS, etc.) to a direction register * the read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. Do not write 1 to bit 0 of the port P4 direction register (address 00091.) Serial I/O When using an external clock, input H to the external clock input pin and clear the serial |/O interrupt request bit before executing a serial !/O transfer. When using the internal clock, set the synchronization clock to internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer. instruction Execution Timing The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cy- cles needed to execute an instruction. , The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the Xi or Xcin frequency. At the STP Instruction Release At the STP instruction release, all bits of the timer 12 mode register are cleared. The Xcour drivability selection bit (the CPU mode register). is set to 1 (high drive) in order to start oscillating. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(Xjy) is 500kHz.or more during an A-D conversion. Do not execute the STP or WIT instruction during A-D con- version. 2430 PRMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS . The following are necessary when ordering a mask ROM production: . (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) If required, specify the following option on the Mask Con- tirmation Form: * Operation start mode switching option ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM program- mer in the user ROM area. Package Name of Programming Adapter 100P6S-A PCA4738F-100A 100D0 PCA4738L-100A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 42 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) SN Verification with PROM programmer Functional check in target device _ Caution, The screening temperature is far higher than the storaga temperature. Never expose to 150T exceeding 100 hours. Fig. 42 Programming and testing of One Time PROM version M! 6249428 002407? 720 oo oats 2431ABSOLUTE MAXIMUM RATINGS MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Symbol Parameter Conditions Ratings Unit Veco Power source voltage , 0.3 to 7.0 v | Vee Pull-down power source voitage Veo40 to Veo+0. 3 v y, Input voltage P19-P17, P29-P27, P4;-P4;, P5p-P5z, 0.3 to Voo+0.3 | Vv P69-P6;, P7p-P77, PAg-PA, PBp, PB vi Input voltage P4p 0.3 to Voo+0. 3 v vi Input voltage P89-P87, PQ-P9, All voltages are based on Vgs. Veco40 to Vec+0. 3 Vv Vv Input voltage RESET, Xin Output transistors are cut off. 0.3 ta Vec+0. 3 Vv Vv, Input voltage Xow 0. 3 to Veco +0. 3 Vv Vo Output voltage Pepe, eve, Voo40 to Veo-+0. 3 v Output voltage P19-P17, P2o-P27, P4,-P47, PSp-P5z, Vo P6o-P67, P7o-P77, PAg-PAz, Xour, Xcour 0. 3 to Vee +0. 3 v Pq Power dissipation Tag = 2 600 mw Topr__ Operating temperature 10 to 85 c Tstg Storage temperature 40 to 125 Cc RECOMMENDED OPERATING CONDITIONS (vce = 4.0 to5.5V, Ta = 10 to 85, unless otherwise noted) Limits Symbol Parameter ~ Unit Min. Typ. Max. High-speed operation mode 4.0 5.0 5.5 Vee Power source voltage Low-speed operation mode 2.8 5.0 5.5 v Vss Power source voltage 0 Vv Vee Pull-down power source voltage Voo38 Veco Vv Vrer Reference input voltage 2 Voc v AVss Analog power source voltage 0 Vv Via Analog input voltage 0 Veco Vv H* input voltage P1o-Pt7, P4y-P47, P5p-P57, Vin P6o-P67, P7o-P77, PAo-PAz, 0. 75Vcc! Vee Vv PBo, PB: Vin H input voltage P29-P27 0. 4Vecg Veco Vv Vin H input voltage P4 0. 75Vec Voc v Vin H input voltage P8)-P87, P9g-P95 0. 8Vcc Voc Vv Vin H" input voltage RESET 0. 8Vec Voc v Vin H input voltage Xi, Xow 0. 8Vcc Voc Vv Vin L input voltage P1o-P17, P4;-P47, P5o-P57, P6p-P67, 0 0. 25Ve0 Vv P?o-P77, PAo-PA7, PBo, PB; Vin L input voltage P29-P2; 0 0.16Vec Vv Vie L input voltage P4y 0 0, 25Voc v Vie L input voltage P8-PB;7, P9)-P9, 0 0. 2Vec Vv Vie L input voltage RESET 0 0. 2V6c Vv Vin L input voltage Xiw, Xcm 0 0. 2Vec Vv M8 6249828 0024078 bh? 2432 | aeMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS (vcc=4.0 to 5. 5v, Ta=10 to 85C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. H total peak output current POo-PQ;, P19-P't7, 2 loupeak) {Note 1) P29-P 27, P39-P37, 240 mA P8-P8;, PQg-P97 Elonipeak) H" total peak output current P4,-P47, P69-P67, 60 mA (Note 1) P7y-P77, PAg-PAz L total peak output current Pto-P17, P29-P27, P4,-P47, Sloupeak) P5o-P57, P6,-P67, 100 mA (Note 1) P7o-P77, PAo-PAz 2 loupeak)| L total peak output current PB) (Note 1) 3.0 mA H" total average output currant POo-PO;, P1p-P17, E lonavg) (Note 1) P2g-P27, P3p-P3z, 120 mA P8-P87, P99-P9; 2 loncavg) | H total average output current P4,-P47, PBp-P67, 30 mA (Note 1) P7o-P77, PAp-PAz : L total average output current Piq-P17, P29-P27, P4,-P47, P5p-P5;, Zlouavg) noupe, oer 50 mA (Note 1) PAg-PA7 Zloicavg) | L total average output current P& (Note 1) 1.5 mA lon(peak) H" peak output current POQ9-P07, P3p-P37, P&y-P8;, 40 mA (Note 2) P%-P9, H" peak output current P19-P17, P2o-P27, P4;-P4z, loncpeak) (Note 2) P6-P6;, P7c-P72, PAs:PA TIO] ma o oO 7 7 louipeak) L peak output current P19-P17, P2p-P2;, P4,-P47, 10 mA (Note 2) P6,-P6;, P79-P77, PAg-PA; lou(peak)| L" peak output current P5o-P5; (Note 2) 10 mA loccpeak)| L peak output current P69 (Note 2) 3.0 mA lon(avg? H average output current POo-P02, P39-P37, 18 mA (Note 3) P8y-P87, P&e-P9; loncavg) H average output current P19-P17, P29-P2;, P4,-P47, 5.0 mA (Note 3) Pp-P6;, P79-P77, PAp-PAr L average output current P1p-P17, P29-P2;, loutavg) (Note 3) P41-P4z, P6;-P6;, 5.0 mA P7o-P77, PAg-PAz loucavg) | L average output current P59-P5, (Note 3) 5.0 mA lo_cavg) | L average output current PG) = -( Note 3) 1.5 mA 4(CNTRo) | Clock input frequency for timers 2 and 4 250 kHz f(CNTR,) | (duty cycte 50%) (Xin Main clock input oscillation frequency (Note 4) 8.4 MHz f(Xcin) __| Sub-clock input oscillation frequency (Note 4, Note 8) 32. 768 50 kHz Note 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current Is an average value measured over 100ms. The total peak current is the peak value of all the currents. om & wh frequency f(Xow) is less than f(Xjy}/3. The peak output current is the peak-current flowing in each port. . The average output current in an average value measured over 100ms. . When the oscillation frequency has a duty cycle of 50%. . When using the microcomputer in low-speed operation mode, make sure that the sub-clock input Me 6249828 0024079 ST3 aa ee 2433MITSUBISHI MICROCOMPUTERS | 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (vec = 4.0 to5. 5v, Tg = 10 to 85T, unless otherwise noted) - Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Von H output voltage POQg-P07, P3p-P37, P8a-P8, low 18mA . Veo2.0 Vv PQo-P9, . : Von H" output voltage P19-P17, P2g-P2;, P4,-P47, lon=10miA Veo~2.0 v P8o-P67, P7o-P77, PAp-PAz . L output voltage P1p-P1z, P29-P27, P4,-P47, Vor P5g-P5;, P6)-P67, P7o-P77, lo =10mA . 2.0 v " PAo-PA; Vor L" output voltage P6y lop =1.5mA 0.5 Vv Vr4-Vr- Hysteresis INToINTs, Sit, Swe, Scuxts Scuxa When using a non-port function 0.4 Vv CNTRo, CNTR; Vr4Vr | Hysteresis RESET, Xi RESET Vec=2. 8V to 5. 5V 0.5 v V14Vy | Hysteresis Xon 0.5 Vv he H input current P19-P17, P2o-P27, P41-P47, P5o-P5;, Vi=Voe 5.0 BA P6p-P67, P7o-P77, PAp-PAz, PBo, PB: lw H input current P4p Vi=Veco , 5.0 uA lie H" input current P8-P8;, P99-P93 (Note 1) Vi=Voe 5.0 HA ling H Input current RESET, Xow | Mi=Voc 5.0 BA lina H Input current Xin Vi=Voc 4.0 uA hn L* input current P19-P17, P29-P27, P4;-P47, PSg-P7, Vi=Ves 5.0 BA P6o-P67, P75-P77, PAg-PA7, PBo, PB: : Ie L input current P4y Vi=Vss 5.0 uA ie L" input current P&-P87, P9p-P93 (Note 1) Vi=Vss 5.0 uA hie *L" input current RESET, Xo Vi=Veg 5.0 uA fie L" input current Xin Vi=Vss : 4.0 aA : Vee=Vec36V, lLoap Output load current PO9-PQ,, P3p-P37, P99-P97 Vot=Voo, 150 500 900 BA Output transistors off : Vee=Veco38V, : Output leakage current POo-P0;, P39-P37, P8&-P87, leak 9,-P9, VorVeo38, . | 10 uA Output transistors off (Except for reset) Vaam RAM hold voltage When clack is stopped 2.0 5.5 v * High-speed mode f(Xin) =8. 4MHz : f(Xow) =32kHz 10 20 mA Output transistors off A-D converter operating * High-speed moda ) (Xi) =8. 4MHz (in WIT state) f(Xein) =32kHz 1.5 mA Output transistors off* | A-D converter stopped * Low-speed mode (Xin) = stopped, f(Xow) =32kHz lee Power source current Low-power dissipation mode set , , 60 200 uA (CMg=0) Output transistors off * Low-speed mode {(4in)= stopped *Xom) =32kHz (in WIT state) 2 40 uA Low-power dissipation mode set (CM5=0) Output transistors off All oscillation stopped Tg=25T : 0.1 1.0 (in STP state) - HA Output transistors att | Ta=85C 10 Note 1. Except when reading ports P&yP8; or ports P9p P93. MB 6249828 0024080 215 MITSUBISHI 2-434 ELECTRICMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS (Veo4. 0 to 5. 5V, Veg=0V, Tg=10 to 85C, high-speed operation mode, unless otherwise noted) Limits Symbot Parameter Test conditions Unit Min. Typ. Max. - Resolution 8 Bits - Absolute accuracy (excluding quantization error) Voco=Vaer=5. 12V +1 #2,5 LSB Tconv Conversion time 49 50 te (4) IVAEF Reference input current Vrer=5V 50 150 200 uA Nia Analog port Input current 0.5 5.0 uA Reaover | Ladder resistor 35 kQ TIMING REQUIREMENTS (Vcc =4.0 to 5.5V, Ves = OV, Ta = 10 to 85C, unless otherwise noted) 4 Symbol Parameter Test conditions Limits Unit Min. Typ. Max. tw(RESET) Reset input L pulse width 2.0 us teoan) Main clock input cycle time (Xi input) 9 ns twHOdn) Main clock input H pulse width 40 ns twiouw) Main clock input L" pulse width 40 ns teixcn) Sub-clock input cycle time (Xciw input) 20 us tWH(xew) Sub-clock input H pulse width 5.0 us twicxn) Sub-clock input L pulse width 5.0 us tecontad CNTRo, CNTR; input cycle time 4.0 us twx(entr) CNTRo, CNTR;, input H" pulse width 1.6 us twitcntr) CNTRo, CNTA;, input L pulse width 1.6 BS twrdnt INTp-INT, input H pulse width 80 ns tweunt) INTp-INT, input L pulse width 80 ns tetseik) Serial 1/O clock input cycle time 1.0 us twa (scr) Serial 1/0 clock input H pulse width 400 ns twe(sourd) Serial 1/0 clock input L pulse width 400 ns tsu(serk-Siy)_ | Serial 1/O input setup time 200 ns thc -Siy) Serial \/O input hold time 200 ns SWITCHING CHARACTERISTICS (vcc =4.0105.5V, Ves =0V, Ta = 10 to 85, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. t ys _ te(sern) IWH(ScLK) Serial 1/0 clock output H* pulse width CL=t00pF, RL=1kQ /2160 ns t apr = = tecscir) WL ScLK) Serial (/O clock output L pulse width C.=100pF, RL=1kQ 2-160 ns tdisoux-Sour? Serial |/O output delay time 0. et seri) ns tvisorxSoyr) | Seriat /O output hold time : 0 ns tise) Serial 1/O clock output falling time C.=100pF, RL=1k2 40 ns. P-channel high-breakdown voltage output rising time t - CL=100pF, Vee=Vec36V 55 n *(Pch-strg) (Note 1) L Pp ce=Voc Ss P-channel high-breakdown voltage output rising time te Pch-weak) CL=100pF, Vee=Vec36V 1.8 us (Note 2) Note 1. When bit 0 of the high-breakdown voltage port contro! register (address 0038,,) is at 0. 2. When bit 0 of the high-breakdown voltage port control register (address 0038,,) is at 1. MB 62498286 002408) 15) oes esMITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PSe/Scrne Re Serial 1/O clock output P5o/Souxi port : P-channel a I C. output port Note : Port P8 has no internal pull-down resistors and external resistors should be used if necessary. Fig. 43 Output switching characteristics measurement circuit MB 62498ces OOekv04e O96 2~ 436 ate ISR Timing Chart CNTRo, CNTR, INTp-INT, RESET Xm Seuk Sout MB 6249824 MITSUBISHI MICROCOMPUTERS 3818 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | tecentR) twu(enta) 1 | fwi(cnTR) 0. 8Vec 0.2V h 2Vce 1 twHcinT) . wont) | 0. 8Vec 0.2v Veg \ twrneseT) ' 0. 8Vec 0. 2Vce lL teouny twHGun) twrow) twH(xcn) tecrcins | fox) tetseu) tf twusorn) tr twrisein) 0. BY, NY 0. 2Ve 1 ome ee, tsu(sin-Scux) thiscix-Swn) KW F'0. 8Vcg | 0. 2Vcc PERE ROK tdsoux-Sour) tW(SeLkSour) 0024083 Teh oe est 2437