ISD2100 DATASHEET ISD2100 Digital ChipCorder with Multi Time Programming and Digital Audio Interface -1- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET TABLE OF CONTENTS 1 GENERAL DESCRIPTION .............................................................................................................. 3 2 FEATURES ...................................................................................................................................... 3 3 BLOCK DIAGRAM ........................................................................................................................... 4 4 PINOUT CONFIGURATION ............................................................................................................ 5 5 PIN DESCRIPTION .......................................................................................................................... 6 6 SPI INTERFACE .............................................................................................................................. 7 7 ANALOG AND DIGITAL SIGNAL PATH ........................................................................................ 10 7.1.1 7.1.2 8 PWM Speaker Driver ..................................................................................................................... 10 Internal Oscillator ......................................................................................................................... 10 ISD2100 MEMORY MANAGEMENT ............................................................................................. 10 8.1 MESSAGE MANAGEMENT ....................................................................................................................... 10 8.1.1 Voice Prompts ................................................................................................................................ 10 8.1.2 Voice Macros ................................................................................................................................. 10 8.1.3 GPIO Voice Trigger Macros: ........................................................................................................ 11 9 ELECTRICAL CHARACTERISTICS .............................................................................................. 12 9.1 OPERATING CONDITIONS ........................................................................................................................ 12 9.2 AC PARAMETERS ................................................................................................................................... 12 9.2.1 Internal Oscillator ......................................................................................................................... 12 9.2.2 Speaker Outputs ............................................................................................................................. 12 9.3 DC PARAMETERS ................................................................................................................................... 12 9.3.2 SPI Timing ..................................................................................................................................... 13 10 APPLICATION DIAGRAM .......................................................................................................... 15 11 PACKAGE SPECIFICATION ...................................................................................................... 16 11.1 20 LEAD QFN ......................................................................................................................................... 16 12 ORDERING INFORMATION ...................................................................................................... 17 13 REVISION HISTORY.................................................................................................................. 18 -2- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 1 GENERAL DESCRIPTION The ISD2100 is a digital ChipCorder(R) featuring digital de-compression, comprehensive memory management, flash storage, and integrated digital audio signal paths. This family utilizes flash memory to provide non-volatile audio playback with duration up to 30 seconds (based on 8kHz/4bit ADPCM) for a single-chip solution. Unlike the MLS ChipCorder series, this device provides higher sampling frequency and a signal path with SNR equivalent to 12-bit resolution. The ISD2100 can take digital audio data via SPI interface. When SPI interface is chosen, the sample rate of the audio data sent must be one of the ISD2100 supported sample rates. The ISD2100 has built-in speaker driver output. 2 FEATURES * Duration o 30 seconds based on 8kHz/4bit ADPCM (ISD2130) Audio Management o Store pre-recorded audio (Voice Prompts) using high quality digital compression o Use a simple index based command for playback o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration of the device and play back Voice Prompts sequences. Sample Rate o 7 sampling frequencies such as 4, 5.3, 6.4, 8, 12.8, 16 and 32 kHz are available. Compression Algorithms o -Law: 6, 7 or 8 bits per sample o Differential -Law: 6, 7 or 8 bits per sample o PCM: 8, 10 or 12 bits per sample o Enhanced ADPCM: 2, 3, 4 or 5 bits per sample o Variable-bit-rate optimized compression. This allows best possible compression given a metric of SNR and background noise levels. Oscillator o Internal oscillator with internal reference: with 1% deviation at room temperature. Output o PWM: Class D speaker driver to direct drive an 8 speaker or buzzer I/Os o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data o 6 general purpose I/O pins that share SPI interface. One 8-bit Volume Controls set by SPI command. Operating Voltage: 2.7-3.6V Package: green, 20L-QFN Temperature Options: o Industrial: -40C to 85C * * * * * * * * * * -3- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 3 BLOCK DIAGRAM Digital Signal Path : Digital Filters Re-sampling SPK+ PWM Control Volume Control SPK- De-Compression GPI1 / SCLK SSB GPIO2 / MISO GPIO0 / MOSI GPIO3 / INTB GPIO4 / RDY/BSYB GPIO5 SPI & GPIO Interface Memory Management and Command Interpreter Flash Memory Controller Flash Memory Figure 3-1 ISD2100 Block Diagram -4- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET SSB 3 MOSI / GPIO0 4 VSSD 5 NC NC NC NC 17 16 ISD2100 ISD2130 QFN-20 6 7 8 9 10 VCCD_PWM 2 18 SPK- SCLK / GPI1 19 VSSD_PWM 1 20 SPK+ MISO / GPIO2 NC PINOUT CONFIGURATION VCCD_PWM 4 15 GPIO5 14 VCCD 13 NC 12 RDY/BSYB / GPIO4 11 INTB / GPIO3 Figure 4-1 ISD2100 20-Lead QFN Pin Configuration. -5- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 5 PIN DESCRIPTION Pin Number Pin Name I/O Function 1 MISO / GPIO2 O Master-In-Slave-Out. Serial output from the ISD2100 to the host. This pin is in tri-state when SSB=1. Can be configured as a general purpose I/O pin. 2 SCLK / GPI1 I Serial Clock input to the ISD2100 from the host. Can be configured as a general purpose input pin. 3 SSB I Slave Select input to the ISD2100 from the host. When SSB is low device is selected and responds to commands on the SPI interface. 4 MOSI / GPIO0 I Master-Out-Slave-In. Serial input to the ISD2100 from the host. Can be configured as a general purpose I/O pin. 5 VSSD I Digital Ground. 6 VCCD_PWM I Digital Power for the PWM Driver. 7 SPK+ O PWM driver positive output. This SPK+ output, together with SPK- pin, provide a differential output to drive 8 speaker or buzzer. During power down this pin is in tri-state. 8 VSSD_PWM I Digital Ground for the PWM Driver. 9 SPK- O PWM driver negative output. This SPK- output, together with SPK+ pin, provides a differential output to drive 8 speaker or buzzer. During power down this pin is tri-state. 10 VCCD_PWM I Digital Power for the PWM Driver. 11 INTB / GPIO3 O Active low interrupt request pin. This pin is an open-drain output. Can be configured as a general purpose I/O pin. 12 RDY/BSYB / GPIO4 O An output pin to report the status of data transfer on the SPI interface. "High" indicates that ISD2100 is ready to accept new SPI commands or data. Can be configured as a general purpose I/O pin. 13 NC 14 VCCD 15 GPIO5 16 NC This pin should be left unconnected. 17 NC This pin should be left unconnected. 18 NC This pin should be left unconnected. 19 NC This pin should be left unconnected. 20 NC This pin should be left unconnected. This pin should be left unconnected. I I/O Digital Power. General purpose I/O pin. -6- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET SPI INTERFACE 6 This is a standard four-wire interface used for communication between ISD2100 and the host. It consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master Out Slave In MOSI), and a data output (Master In Slave Out - MISO). In addition, for some transactions requiring data flow control, a RDY/BSYB signal (pin) is available. The ISD2100 supports SPI mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data is sampled at SCLK rising edge. A SPI transaction begins on the falling edge of SSB and its waveform is illustrated below: SSB SCLK MISO MOSI Z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 X S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 X C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X Figure 6-1 SPI Data Transaction. A transaction begins with sending a command byte (C7-C0) with the most significant bit (MSB - C7) sent in first. During the byte transmission, the status (S7-S0) of the device is sent out via the MISO pin. After the byte transmission, depending upon the command sent, one or more bytes of data will be sent via the MISO pin. RDY/BSYB pin is used to handshake data into or out of the device. Upon completion of a byte transmission, RDY/BSYB pin could change its state after the rising edge of the SCLK if the built-in 32byte data buffer is either full or empty. At this point, SCLK must remain high until RDY/BSYB pin returns to high, indicating that the ISD2100 is ready for the next data transmission. See below for timing diagram. -7- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET TR / B SSB SCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RDY/BSYB =1 MISO MOSI Z =1 X PD RDY INT FULL X VG BUF BSY FUL X C7 C2 C6 C5 C4 C3 C1 CMD BSY C0 PD RDY INT FULL X VG BUF CMD BSY FUL BSY D7 D2 D6 D5 D4 D3 D1 D0 X Figure 6-2 RDY/BSYB Timing for SPI Writing Transactions. If the SCLK does not remain high, RDY bit of the status register will be set to zero and be reported via the MISO pin so the host can take the necessary actions (i.e., terminate SPI transmission and retransmit the data when the RDY/BSYB pin returns to high). For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from ISD2100, MISO is used to read the data; therefore, the host must monitor the status via the RDY/BSYB pin and take the necessary actions. The INT pin will go low to indicate (1) data overrun/overflow when sending data to the ISD2100; or (2) invalid data from ISD2100. See Figure 6-3 for the timing diagram. -8- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET TR / B SSB SCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RDY/BSYB =1 MISO MOSI Z =0 X PD RDY INT FULL X VG BUF CMD PD RDY INT FULL X BSY FUL BSY X C7 C2 C6 C5 C4 C3 C1 C0 D7 D6 D5 D4 D3 VG BUF CMD BSY FUL BSY D2 D1 D0 X INT Figure 6-3 SPI Transaction Ignoring RDY/BSYB -9- Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET ANALOG AND DIGITAL SIGNAL PATH 7 7.1.1 PWM Speaker Driver PWM driver output pins SPK-, together with SPK+ pin, provides a differential output to drive 8 speaker or buzzer. During power down these pins are in tri-state. 7.1.2 Internal Oscillator The ISD2100 device has an internal oscillator that requires no external resistor to operate, however the ISD2100 also provide an internal oscillator with external reference resistor (Rosc) that has an accuracy of 5% with selectable master sample rate 4Khz, 5.33Khz, 6.4khz, 8Khz, 12.8Khz, 16Khz, and 32Khz. 8 ISD2100 MEMORY MANAGEMENT The ISD2100 employs several memory management techniques to make audio playback transparent to the host controller. The address space of the ISD2100 starts at address zero of the internal memory. 8.1 MESSAGE MANAGEMENT The message management schemes implemented on the ISD2100 are: 1. Voice Prompts: A collection of pre-recorded audio that can be played back using the PLAY_VP SPI command or Voice Macros. 2. Voice Macros: A powerful voice script allowing users to create custom macros to play Voice Prompts, insert silence and configure the device. Voice Macros are executed with a single SPI command. 3. User Data: Memory sectors defined and allocated by the users for use in other applications 8.1.1 Voice Prompts Voice prompts are pre-recorded audio of any length, from short words, phrases or sound effects to long passages of music. These Voice Prompts can be played back in any order as determined by the users and applications. A Voice Prompt consists of two components: 1. An index pointing to the pre-recorded audio 2. Pre-recorded audio 8.1.2 Voice Macros Voice Macros are a powerful voice script that allows users to customize their own play patterns such as play Voice Prompts, insert silence, change the master sample clock, powerdown the device and configure the signal path, including gain and volume control. - 10 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 8.1.3 GPIO Voice Trigger Macros: The ISD2100 GPIO flexibility allows the user to configure the device to triggers a voice macro in many different combinations for a push button application. Below is some possible configuration of the GPIO pins using Voice trigger macros? 1. Single Hi-Low trigger sequence through messages A high to low trigger on any GPIO 0~ 5 will start to play Voice Macro 3, 4, 5, 6 and back to Voice Macro 3. Each Voice Macro points directly or indirectly to voice prompt One, Two, Three, Four. 2. Single Hi-Low trigger Loop unless interrupted by another Trigger A single trigger on any GPIO 0~ 5 will loop through several messages until it is interrupted by another trigger to stop playback, the device goes to power down after. 3. Single Hi-Low trigger through messages uninterruptable by another Trigger A single trigger on any GPIO 0~ 5 will sequence through several messages until all messages are played. The playback cannot be interrupted by another trigger on any GPIO 0~ 5 to stop playback. 4. Single Hi-Low trigger sequences through messages with silence (pause) in between each message. A single trigger on any GPIO 0~ 5 will sequence through several messages with pause in between each message. A 256ms play silence added in between each message to create a short pause for natural sound. All messages are played in a loop indefinitely until another trigger on any GPIO 0~ 5 to stop playback. 5. Level Hold trigger sequence through messages interruptible A Level Hold on any GPIO 0~ 5 will sequence through several messages with pause in between each message. A 32ms play silence added in between each message to create a very short pause for natural sound. Playback stops when GPOI is released or all messages are played. 6. Level Hold trigger Loop through messages interruptible A Level Hold on any GPIO 0~ 5 will loop through several messages with pause in between each message. A 32ms play silence added in between each message to create a very short pause for natural sound. Playback stops when GPOI is released or interrupted or by another GPIO trigger. - 11 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 9 ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS 9.1 OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS) CONDITIONS VALUES Operating temperature range (Case temperature) Supply voltage (VDD) Ground voltage (VSS) Input voltage (VDD) -40C to +85C [1] +2.7V to +3.6V [2] 0V [1] 0V to 3.6V Voltage applied to any pins NOTES: 9.2 (VSS -0.3V) to (VDD +0.3V) [1] VDD = VCCA = VCCD = VCCPWM [2] VSS = VSSA = VSSD = VSSPWM AC PARAMETERS 9.2.1 Internal Oscillator PARAMETER SYMBOL MIN TYP MAX UNITS CONDITIONS Internal Oscillator with internal reference FINT -1% 65.536 MHz +1% MHz Vdd = 3V. At room temperature 9.2.2 Speaker Outputs PARAMETER SYMBOL SNR, Memory to SPK+/SPK- SNRMEM_SPK Output Power POUT_SPK VCC=3.0 THD, Memory to SPK+/SPK- THD % Minimum Load Impedance RL(SPK) Notes: MIN TYP[1] MAX 60 0.4 UNITS CONDITIONS dB Load 150 [2][3] W Load 8 [2] Load 8 [2] <1% 4 8 [1] Conditions Vcc=3V, TA=25C unless otherwise stated. Based on 12-bit PCM. [3] All measurements are C-message weighted. [2] 9.3 DC PARAMETERS MIN TYP [1] PARAMETER SYMBOL Supply Voltage VDD 2.7 3.6 V Input Low Voltage VIL VSS-0.3 0.3xVDD V Input High Voltage VIH 0.7xVDD VDD V - 12 - MAX UNITS CONDITIONS Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET Output Low Voltage VOL VSS-0.3 0.3xVDD V IOL = 1mA Output High Voltage VOH 0.7xVDD VDD V IOH = -1mA INTB Output Low Voltage VOH1 0.4 V Playback Current IDD_Playback 5 Standby Current ISB 1 Input Leakage Current IIL [1] Notes: 9.3.2 mA No Load 10 A VDD= 3.6V 1 A Force VDD Conditions VDD=3V, TA=25C unless otherwise stated SPI Timing TSSBHI SSB TSSBS TSSBH TSCK TRISE TFALL SCLK TSCKH TSCKL MOSI TMOS TMOH TZMID TMIZD MISO TMID TCRBD TRBCD RDY/BSYB Figure 11-1 SPI Timing SYMBOL DESCRIPTION MIN TYP MAX UNIT TSCK SCLK Cycle Time 60 --- --- ns TSCKH SCLK High Pulse Width 25 --- --- ns TSCKL SCLK Low Pulse Width 25 --- --- ns TRISE Rise Time for All Digital Signals --- --- 10 ns - 13 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET SYMBOL TFALL DESCRIPTION Fall Time for All Digital Signals st MIN TYP MAX UNIT --- --- 10 ns TSSBS SSB Falling Edge to 1 SCLK Falling Edge Setup Time 30 --- --- ns TSSBH Last SCLK Rising Edge to SSB Rising Edge Hold Time 30ns --- 50us --- TSSBHI SSB High Time between SSB Lows 20 --- --- ns TMOS MOSI to SCLK Rising Edge Setup Time 15 --- --- ns TMOH SCLK Rising Edge to MOSI Hold Time 15 --- --- ns TZMID Delay Time from SSB Falling Edge to MISO Active -- -- 12 ns TMIZD Delay Time from SSB Rising Edge to MISO Tri-state -- -- 12 ns TMID Delay Time from SCLK Falling Edge to MISO --- --- 12 ns TCRBD Delay Time from SCLK Rising Edge to RDY/BSYB Falling Edge -- -- 12 ns TRBCD Delay Time from RDY/BSYB Rising Edge to SCLK Falling Edge 0 -- -- ns - 14 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 10 APPLICATION DIAGRAM The following applications example is for references only. It makes no representation or warranty that such applications shall be suitable for the use specified. Each design has to be optimized in its own system for the best performance on voice quality, current consumption, functionalities and etc. V CCD 14 V CCD uF 0 .01 uF 4.7 uF 0 .1 uF 10 V SSD 5 V CCD 6 ISD 2130 QFN - 20 V CCD _ PWM V CCD _ PWM 10 V SSD _ PWM SPK + V CCD SPI Type -III 10 K 1 2 3 4 11 Data flow control SPK MISO / GPIO 2 SCLK / GPI 1 SSB MOSI / GPIO 0 INTB / GPIO 3 RDY /BSYB / GPIO 4 GPIO 5 0 001 .uF 8 7 9 15 12 Figure 12-1 ISD2100 Application Diagram The above application examples are for references only. It makes no representation or warranty that such applications shall be suitable for the use specified. Each design has to be optimized in its own system for the best performance on voice quality, current consumption, functionalities and etc. - 15 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 11 11.1 PACKAGE SPECIFICATION 20 LEAD QFN TOP VI EW 15 BOTTOM VI EW 11 11 10 10 16 20 16 20 6 6 1 15 5 5 - 16 - 1 Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 12 ORDERING INFORMATION I21XX X Y I R R: Tape and Reel Temperature I: Industrial -40C to 85C Duration 30: 30 Seconds * Based on 8kHz/4bit ADPCM Package Option Y: green Package Type Y: 20L-QFN - 17 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET 13 REVISION HISTORY Version Date Description 0.2 Jan 29, 2009 Initial draft. 0.45 August 5, 2009 Add Wake-Up VM description 0.46 November 11, 2009 Add Checksum Description 0.48 January 9, 2010 Simplify all Block diagrams 0.51 Feb 4, 2010 Update description - 18 - Publication Release Feb 9, 2010 Revision 0.51 ISD2100 DATASHEET Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. The contents of this document are provided "AS IS", and Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if Nuvoton has been advised of the possibility of such damages. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD(R) ChipCorder(R) product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change without notice. Copyright(c) 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder(R) and ISD(R) are trademarks of Nuvoton Electronics Corporation. All other trademarks are properties of their respective owners. Headquarters Nuvoton Technology Corporation America Nuvoton Technology (Shanghai) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.nuvoton.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.nuvoton-usa.com/ 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office Nuvoton Technology Corporation Japan Nuvoton Technology (H.K.) Ltd. 9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 19 - Publication Release Feb 9, 2010 Revision 0.51