ISD2100 DATASHEET
Publication Release Feb 9, 2010
- 1 - Revisi on 0.51
ISD2100
Digital ChipCorder
with
Multi Time Programming and Digital Audio Interface
ISD2100 DATASHEET
Publication Release Feb 9, 2010
- 2 - Revisi on 0.51
TABLE OF CONTENTS
1 GENERAL DESCRIPTION .............................................................................................................. 3
2 FEATURES ...................................................................................................................................... 3
3 BLOCK DIAGRAM ........................................................................................................................... 4
4 PINOUT CONFI G URATI O N ............................................................................................................ 5
5 PIN DESCRIPTION .......................................................................................................................... 6
6 SPI INTERFACE .............................................................................................................................. 7
7 ANALOG AND DIGITAL SIGNAL PATH ........................................................................................ 10
7.1.1 PWM Speaker Driver ..................................................................................................................... 10
7.1.2 Internal Oscillator ......................................................................................................................... 10
8 ISD2100 MEMORY MANAGEMENT ............................................................................................. 10
8.1 MESSAGE MANAGEMENT ....................................................................................................................... 10
8.1.1 Voice Prompts ................................................................................................................................ 10
8.1.2 Voice Macros ................................................................................................................................. 10
8.1.3 GPIO Voice Tr igger Macr os: ........................................................................................................ 11
9 ELECTRICAL CHARACT ERISTICS .............................................................................................. 12
9.1 OPERATING CONDITIONS ........................................................................................................................ 12
9.2 AC PARAMETERS ................................................................................................................................... 12
9.2.1 Internal Oscillator ......................................................................................................................... 12
9.2.2 Speaker Outputs ............................................................................................................................. 12
9.3 DC PARAMETERS ................................................................................................................................... 12
9.3.2 SPI Timing ..................................................................................................................................... 13
10 APPLICATION DIAGRAM .......................................................................................................... 15
11 PACKAGE SPECIFICATION ...................................................................................................... 16
11.1 20 LEAD QFN ......................................................................................................................................... 16
12 ORDERING INFORMATION ...................................................................................................... 17
13 REVISION HISTORY .................................................................................................................. 18
ISD2100 DATASHEET
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- 3 - Revisi on 0.51
1 GENERAL DESCRIPTION
The ISD2100 is a digital ChipCorder® featuring digital de-compression, comprehensive memory
management, flash storage, and integrated digital audio signal paths. This family utilizes flash
memory to provide non-volatile audio playback with duration up to 30 seconds (based on 8kHz/4bit
ADPCM) for a single-chip solution.
Unlike the MLS ChipCorder series, this device provides higher sampling frequency and a signal path
with SNR equival ent to 12-bit resolution.
The ISD2100 can take digital audio data via SPI interface. When SPI interface is chosen, the sample
rate of the audio dat a sent must be one of t he ISD2100 supporte d sample rates.
The ISD2100 has built-in speaker driver output.
2 FEATURES
• Duration
o 30 seconds based on 8kHz/4bit A DP CM (ISD2130)
• Audio Management
o Store pre-recorde d audio (Voice Prompts) using high quali ty digital compre ssion
o Use a simple index based command for pl ayback
o Execute pre-programmed macro sc ripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences.
• Sample Rate
o 7 sampling frequencies such as 4, 5.3, 6.4, 8, 12.8, 16 and 32 kHz are available .
• Compression Algorithms
o µ-Law: 6, 7 or 8 bits per sample
o Differential µ-Law: 6, 7 or 8 bits per sample
o PCM: 8, 10 or 12 bits per sample
o Enhanced ADPCM: 2, 3, 4 or 5 bits per sampl e
o Variable-bit-rate optimized compression. This allows best pos sible comp res sion giv en a
metric of SNR and b ackground noise levels.
• Oscillator
o Internal oscillator with internal ref erence: with ±1% deviation at room temperature.
• Output
o PWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer
• I/Os
o SPI interface: MISO, MOSI, S CLK , SSB for commands and digital audio data
o 6 general purpos e I/O pins that shar e SPI interface.
• One 8-bit Volume Controls set by SPI command.
• Operating Volt age: 2.7-3.6V
• Package: green, 20L-QFN
• Temperature Opti ons:
o Industrial: -40°C to 85°C
ISD2100 DATASHEET
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- 4 - Revisi on 0.51
3 BLOCK DIAGRAM
Digital Signal Path
:
Digital
Filters
Re
-
sampling
Volume Control
Control
De
-
Compression
Flash Memory
Controller
Flash Memory
SPI
&
GPIO
Interface
Memory Management
and Command
Interpreter
SPK
+
SPK
-
SCLK
GPI
1
/
SSB
MISO
GPIO
2
/
MOSI
GPIO
0
/
INTB
GPIO
3
/
RDY
/
BSYB
GPIO
4
/
GPIO
5
Figure 3-1 ISD2100 Block Diagram
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4 PINOUT CONFI GURATION
Figure 4-1 ISD2100 20-Lead QFN P i n Conf i guration.
2
3
4
5
6 7 8 9 10
1
11
12
13
14
15
1617181920
V
SSD
NC
MOSI / GPIO0
SSB
SCLK / GPI1
MISO / GPIO2
V
CCD
_PWM
V
SSD
_PWM
SPK+
V
CCD
_PWM
INTB / GPIO3
RDY/BSYB / GPIO4
V
CCD
GPIO5
NC
NC
NC
NC
NC
ISD2130
QFN-20
SPK-
ISD2100
ISD2100 DATASHEET
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5 PIN DESCRIPTI ON
Pin
Number Pin Name I/O Function
1 MISO /
GPIO2 O Master-In-Slave-Out. Serial output f rom the ISD2100 to the host. This
pin is in tri-state when SSB=1.
Can be configured as a general purpo se I/O pin.
2 SCLK / GPI1 I Serial Clock input to the ISD2100 from the host .
Can be configured as a general purpo se input pin.
3 SSB I Slave Select input to the ISD2100 from the host. When SSB is low
device is select ed and responds to commands on the SP I interface.
4 MOSI /
GPIO0 I Master-Out-Slave-In. Serial input to the ISD2100 from the host.
Can be configured as a general purpose I/O pin.
5 VSSD I Digital Ground.
6 VCCD_PWM I Digital Power f or the PWM Driver.
7 SPK+ O PWM driver posit i ve output. This SPK+ output, together with SPK- pin,
provide a different i al output to driv e 8Ω speaker or buzzer. Du ri ng
power down this pin is in tri-state.
8 VSSD_PWM I Digital Ground f or the PWM Driver.
9 SPK- O PWM driver negat i ve output. This SPK- output, together with SPK+
pin, provides a di fferential output to drive 8Ω speaker or buzzer.
During power down this pin is tri-state.
10 VCCD_PWM I Digital Power f or the PWM Driver.
11 INTB /
GPIO3 O Active low interrupt request pin. This pin is an open-drain output.
Can be configured as a general purpo se I/O pin.
12 RDY/BSYB /
GPIO4 O An output pin t o report the status of data transfer on the SPI interface.
“High” indicates t hat ISD2100 is ready to accept new SP I commands
or data.
Can be configured as a general purpo se I/O pin.
13 NC This pin should be left unconnected.
14 VCCD I Digital Power.
15 GPIO5 I/O General purpose I/O pin.
16 NC This pin should be left unconnected.
17 NC This pin should be left unconnected.
18 NC This pin should be left unconnected.
19 NC This pin should be left unconnected.
20 NC This pin should be left unconnected.
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6 SPI INTERFACE
This is a standard four-wire interface used for communication between ISD2100 and the host. It
consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master Out Slave In -
MOSI), and a data output (Master In Slave Out - MISO). In addition, for some transactions requiring
data flow control, a RDY/BSYB signal (pin) is available.
The ISD2100 supports SPI mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data is
sampled at SCLK rising edge. A SPI transaction begins on the falling edge of SSB and its waveform is
illustrated bel ow:
0123456701234567
SSB
SCLK
MISO
MOSI XC7 C6 C5XC4 C3 C2 C1 C0
S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Z X
Figure 6-1 SPI Dat a Transaction.
A transaction begins with sending a command byte (C7-C0) with the most significant bit (MSB – C7)
sent in first. During the byte transmission, the status (S7-S0) of the device is sent out via the MISO
pin. After the byte transmission, depending upon the command sent, one or more bytes of data will be
sent via the MISO pi n.
RDY/BSYB pin is used to handshake data into or out of the device. Upon completion of a byte
transmission, RDY/BSYB pin could change its state after the rising edge of the SCLK if the built-in 32-
byte data buffer is either full or empty. At this point, SCLK must remain high until RDY/BSYB pin
returns to high, indicating that the ISD2100 is ready for the next data transmission. See below for
timing diagram.
ISD2100 DATASHEET
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01234567 01234567
SSB
SCLK
MISO
MOSI XC7 C6 C5XC4 C3 C2 C1 C0
PD RDY INT FULL X
VG
BSY BUF
FUL CMD
BSY
PD RDY INT FULL X
VG
BSY BUF
FUL CMD
BSY
D7 D6 D5 D4 D3 D2 D1 D0
Z X
RDY/BSYB
BR
T
/
=1 =1
Figure 6-2 RDY/BSYB Timing for SPI Writing T ransactions.
If the SCLK does not remain high, RDY bit of the status register will be set to zero and be reported via
the MISO pin so the host can take the necessary actions (i.e., terminate SPI transmission and re-
transmit the data when the RDY/ BSYB pin returns to high).
For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from ISD2100, MISO is used to
read the data; therefore, the host must monitor the status via the RDY/BSYB pin and take the
necessary acti ons.
The INT pin will go low to indicate (1) data overrun/overflow when sending data to the ISD2100; or (2)
invalid data from ISD2100. See Figure 6-3 for the timing diagram .
ISD2100 DATASHEET
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- 9 - Revisi on 0.51
0123456701234567
SSB
SCLK
MISO
MOSI
XC7 C6 C5XC4 C3 C2 C1 C0
PD RDY INT FULL X
VG
BSY BUF
FUL CMD
BSY
PD RDY INT FULL X
VG
BSY BUF
FUL CMD
BSY
D7 D6 D5 D4 D3 D2 D1 D0
Z X
RDY/BSYB
BR
T
/
=1 =0
INT
Figure 6-3 SPI Transaction Ignoring RDY/BSYB
ISD2100 DATASHEET
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7 ANALOG AND DIGI TAL SIGNAL PATH
7.1.1 PWM Speaker Driv er
PWM driver output pins SPK-, together with SPK+ pin, provides a differential output to drive 8Ω
speaker or buzzer. During power down these pins are in tri-state.
7.1.2 Internal Oscillator
The ISD2100 device has an internal oscillator that requires no external resistor to operate, however
the ISD2100 also provide an internal oscillator with external reference resistor (Rosc) that has an
accuracy of ±5% with selectable master sample rate 4Khz, 5.33Khz, 6.4khz, 8Khz, 12.8Khz, 16Khz,
and 32Khz.
8 ISD2100 MEMORY MANAG EMENT
The ISD2100 employs several memory management techniques to make audio playback transparent
to the host controller. The address space of the ISD2100 starts at address zero of the internal
memory.
8.1 MESSAGE MANAGEMENT
The message management schemes implemented on the ISD2100 are:
1. Voice Prompts: A collection of pre-recorded audio that can be played back using the
PLAY_VP SPI command or Voice Macros.
2. Voice Macros: A powerful voice script allowing users to create custom macros to play Voice
Prompts, insert silence and configure the device. Voice Macros are executed with a single SPI
command.
3. User Data: Mem ory sectors defined and allocated by the users for use in other a ppl ications
8.1.1 Voice Prompts
Voice prompts are pre-recorded audio of any length, from short words, phrases or sound
effects to long passages of music. These Voice Prompts can be played back in any order as
determined by the users and applications. A Voice Prompt consists of two co mponents:
1. An index pointing to the pre-recorded audio
2. Pre-recorded audio
8.1.2 Voice Macros
Voice Macros are a powerful voice script that allows users to customize their own play
patterns such as play Voice Prompts, insert silence, change the master sample clock, power-
down the device and configure the sign al path, including gain and volume control .
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8.1.3 GPIO Voice Trigger Macros:
The ISD2100 GPIO flexibility allows the user to configure the device to triggers a voice macro in many
different combinations for a push button application. Below is some possible configuration of the GPIO
pins using Voice trigger macros?
1. Single Hi-Low trigger sequence through m essa ges
A high to low trigger on any GPIO 0~ 5 will start to play Voice Macro 3, 4, 5, 6 and back to Voice
Macro 3. Each Voice Macro points direc tly or indirectly to voice prompt One, Two, Three, Four.
2. Single Hi-Low trigger Loop unless interrupted by another Trigger
A single trigger on any GPIO 0~ 5 will loop through several messages until it is interrupted by another
trigger to stop playback, the device goes to power down after.
3. Single Hi-Low trigger through messa ges uni nterruptable by another Trigger
A single trigger on any GPIO 0~ 5 will sequence through several messages until all messages are
played. The playback c annot be interrupt ed by another trigger on any GPIO 0~ 5 to stop playback.
4. Single Hi-Low trigger sequences through messages with silence (pause) in between
each message.
A single trigger on any GPIO 0~ 5 will sequence through several messages with pause in between
each message. A 256ms play silence added in between each message to create a short pause for
natural sound. All messages are played in a loop indefinitely until another trigger on any GPIO 0~ 5 to
stop playback.
5. Level Hold trigger sequence through messages interruptibl e
A Level Hold on any GPIO 0~ 5 w ill sequence through several messages with pause in between each
message. A 32ms play silence added in between each message to create a very short pause for
natural sound. Playback stops when GP O I is released or all me ss ages are played.
6. Level Hold trigger Loop t hrough messages interruptible
A Level Hold on any GPIO 0~ 5 will loop through several messages with pause in between each
message. A 32ms play silence added in between each message to create a very short pause for
natural sound. Playback stops when GP OI is released or interrupted or by another GPIO trigger.
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9 ELECTRICAL CHARACT ERISTICS
9.1 OPERATING CONDITIONS
OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)
CONDITIONS VALUES
Operating temperature range (Case temperature) -40°C to +85°C
Supply voltage (VDD) [1] +2.7V to +3.6V
Ground voltage (VSS) [2] 0V
Input voltage (VDD) [1] 0V to 3.6V
Voltage applied to any pins (VSS –0.3V) to (VDD +0.3V)
NOTES: [1] VDD = VCCA = VCCD = VCCPWM
[2] VSS = VSSA = VSSD = VSSPWM
9.2 AC PARAMETERS
9.2.1 Internal Oscillator
PARAMETER SYMBOL MIN TYP MAX UNITS CONDITIONS
Internal Oscillat or with internal
reference FINT -1% 65.536
MHz +1% MHz Vdd = 3V.
At room temperat ure
9.2.2 Speaker Outputs
PARAMETER SYMBOL MIN TYP[1] MAX UNITS CONDITIONS
SNR, Memory to SPK+/SPK- SNRMEM_SPK 60 dB Load 150Ω [2][3]
Output Power POUT_SPK VCC=3.0 0.4 W Load 8Ω [2]
THD, Memory to SPK+/SPK- THD % <1%
Load 8Ω [2]
Minimum Load Impedance RL(SPK) 4 8 Ω
Notes: [1] Conditions Vcc=3V, TA=25°C unless otherwise stated.
[2] Based on 12-bit PCM.
[3] All measurements are C-message weight ed.
9.3 DC PARAMETERS
PARAMETER SYMBOL MIN TYP [1] MAX UNITS CONDITIONS
Supply Voltage VDD 2.7 3.6 V
Input Low Voltage VIL VSS-0.3 0.3xVDD V
Input High Voltage VIH 0.7xVDD VDD V
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Output Low Volt age VOL VSS-0.3 0.3xVDD V IOL = 1mA
Output High Volt age VOH 0.7xVDD VDD V IOH = -1mA
INTB Output Low Volt age VOH1 0.4 V
Playback Current IDD_Playback 5 mA No Load
Standby Current ISB 1 10 µA VDD= 3.6V
Input Leakage Current IIL ±1 µA Force VDD
Notes: [1] Conditions VDD=3V, TA=25°C unless ot herwise stated
9.3.2 SPI Timing
T
RISE
T
FALL
SSB
SCLK
MOSI
MISO
T
SCK
T
SCKH
T
SCKL
T
SSBS
T
SSBH
T
MOS
T
MOH
T
MID
T
SSBHI
T
ZMID
RDY/BSYB T
CRBD
T
RBCD
T
MIZD
Figure 11-1 SPI Timing
SYMBOL DESCRIPTION MIN TYP MAX UNIT
TSCK SCLK Cycle Time 60 --- --- ns
TSCKH SCLK High Pulse Width 25 --- --- ns
TSCKL SCLK Low Pulse Width 25 --- --- ns
TRISE Rise Time for All Digital Signals --- --- 10 ns
ISD2100 DATASHEET
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SYMBOL DESCRIPTION MIN TYP MAX UNIT
TFALL Fall Time for All Digital Signals --- --- 10 ns
TSSBS SSB Falling Edge to 1st SCLK Falling Edge Setup
Time 30 --- --- ns
TSSBH Last SCLK Rising Edge to SSB Rising Edge Hold
Time 30ns --- 50us ---
TSSBHI SSB High Time between S SB Lows 20 --- --- ns
TMOS MOSI to SCLK Rising Edge Setup Tim e 15 --- --- ns
TMOH SCLK Rising Edge to MOSI Hold Ti m e 15 --- --- ns
TZMID Delay Time from SSB Falling Edge to MISO Active -- -- 12 ns
TMIZD Delay Time from SSB Rising Edge to MISO Tri-state -- -- 12 ns
TMID Delay Time from SCLK Falling Edge to MISO --- --- 12 ns
TCRBD Delay Time from SCLK Rising Edge to RDY/BSYB
Falling Edge -- -- 12 ns
TRBCD Delay Time from RDY/BSYB Rising Edge to SCLK
Falling Edge 0 -- -- ns
ISD2100 DATASHEET
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10 APPLICATION DIAGRAM
The following applications example is for references only. It makes no representation or warranty that
such applications shall be suitable for the use specified. Each design has to be optimized in its own
system for the best performance on voice quality, current consumption, f unct ionalities and etc.
MISO
/
GPIO
2
SCLK
/
GPI
1
SSB
MOSI
/
GPIO
0
INTB
/
GPIO
3
RDY
/
BSYB
/
GPIO
4
1
2
3
4
11
12
V
SSD
V
CCD
V
CCD
0
.
1
uF
4.7
uF
V
CCD
6
10
8
V
_
PWM
V
CCD
_
PWM
V
CCD
_
PWM
V
CCD
Ω
10
K
Data flow control
SPI Type
-
III
SPK
+
SPK
-
7
9
GPIO
5
15
14
5
0
.
01
uF
0
.
001
uF
10
uF
ISD
2130
QFN
-
20
Figure 12-1 ISD2100 Applicati on Diagra m
The above application examples are for references only. It makes no representation or warranty that such applications shall be
suitable for the use specified. Each design has to be optimized in its own system for the best performance on voice quality,
current consumption, functionalities and etc.
ISD2100 DATASHEET
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- 16 - Revisi on 0.51
11 PACKAGE SPECIFICATION
11.1 20 LEAD QFN
TOP VI E W B OT T OM V I E W
11
620
15
10
15
16
16
15 11
10
6
51
20
ISD2100 DATASHEET
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- 17 - Revisi on 0.51
12 ORDERING INFO RMATION
I21XX
X Y I R
Package Type
Y: 20L-QFN
Duration
30: 30 Seconds
* Based on 8kHz/4bit ADPCM
Package Option
Y: green
Temperature
I: Industrial -40°C to 85°C
R: Tape and Reel
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13 REVISION HISTORY
Version Date Description
0.2 Jan 29, 2009 Initial draft.
0.45 August 5, 2009 Add Wake-Up V M description
0.46 November 11, 2009 Add Checksum Description
0.48 January 9, 2010 Simplify all Block diagrams
0.51 Feb 4, 2010 Update description
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Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
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Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
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The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
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whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
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The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any
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Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
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The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in
the Nuvoton Reliability Report , and are neither warr ant ed nor guar ant eed by Nuvoton.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information in
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Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
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