Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer DESCRIPTION SA8015 PIN CONFIGURATION The SA8015 is a monolithic low power, high performance frequency synthesizer fabricated in QUBiC BiCMOS technology. It is compatible with the main synthesizer of the SA8025A. Featuring Fractional-N division with selectable modulo 5 or 8 implemented in the Main divider to allow the phase detector comparison frequency to be five or eight times the channel spacing. This feature reduces the overall division ratio yielding a lower noise floor and faster channel switching. The phase detectors and charge pumps are designed to achieve phase detector comparison frequencies up to 5MHz. A four modulus prescaler (divide by 64/65/68/73) is integrated on chip with a maximum input frequency of 1.8GHz at 3V. Programming and channel selection are realized by a high speed 3-wire serial interface. DK Package CLOCK 1 20 VDD DATA 2 19 TEST STROBE 3 18 LOCK VSS 4 17 RF SA8015 RFIN+ 5 RFIN- 6 15 VDDA VCCP 7 14 PHP REFIN 8 13 NC NC 9 12 VSSA 16 RN 11 NC NC 10 FEATURES SR01010 * Operation up to 1.8GHz at 3V * Fast locking by "Fractional-N" divider * Internal charge pump and fractional compensation * 3-line serial interface bus * Low power consumption * Supply voltage range 2.7 to 5.5V * Excellent input sensitivity:VRF IN = -20dBm Figure 1. Pin Configuration APPLICATIONS * PHS (Personal Handy Phone System) * Portable battery-powered radio equipment ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # -40 to +85C SA8015DK SOT266-1 20-Pin Plastic Shrink Small Outline Package (SSOP) ABSOLUTE MAXIMUM RATINGS SYMBOL V VIN VGND PARAMETER Supply voltage, VDD, VDDA, VCCP Voltage applied to any other pin Difference in voltage between ground poins (these pins should be connected together) RATING UNITS -0.3 to +6.0 V -0.3 to (VDD + 0.3) V -0.3 to +0.3 V PTOT Total power dissipation TSTG Storage temperature range -65 to +150 C Operating ambient temperature range -40 to +85 C TA mW NOTE: Thermal impedance (JA) = 117C/W. This device is ESD sensitive. 1995 Sep 1 751 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer PIN DESCRIPTIONS Symbol Pin Description CLOCK 1 Serial clock input DATA 2 Serial data input STROBE 3 Serial strobe input VSS 4 Digital ground RFIN 5 Prescaler positive input RFIN 6 Prescaler negative input VCCP 7 Prescaler positive supply voltage. This pin supplies power to the prescaler and RF input buffer REFIN 8 Reference divider input NC 9 Not connected NC 10 Not connected NC 11 Not connected VSSA 12 Analog ground NC 13 Not connected PHP 14 Phase detector output VDDA 15 Analog supply voltage. RN 16 Charge pump current setting; resistor to VSSA RF 17 Fractional compensation current setting; resistor to VSSA LOCK 18 Lock detector output TEST 19 Test pin; connect to VDD VDD 20 Digital supply voltage. 1995 Sep 1 752 SA8015 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 BLOCK DIAGRAM SA8015 VDD CLOCK SERIAL INPUT + PROGRAM LATCHES DATA STROBE VSS EM FB PR 2 NM2 NM3 NM4 12 8 NM1 2 FB FMOD NF 3 RFin+ 64/65/68/73 PRESCALER MODULUS CONTROL FRACTIONAL ACCUMULATOR MAIN DIVIDERS PRESCALER RFin- RF amp TEST RN 8 CN 2 PHASE DETECTOR EM CHARGEPUMP PHP VCCP EM REFERENCE SELECT NR 12 REFin REFERENCE DIVIDER /2 /2 /2 LOCK VDDA VSSA Figure 2. Block Diagram 1995 Sep 1 753 SR01011 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 DC ELECTRICAL CHARACTERISTICS VDD = VDDA = VCCP = 3V; TA = 25C, unless otherwise specified. SYMBOL PARAMETER VSUPPLY Recommended operating conditions ISTANDBY Total standby supply currents ITOTAL TEST CONDITIONS VCCP = VDD, VDDA VDD LIMITS MIN TYP 2.7 EM = EA = 0, IRN = IRF = IRA = 0 5.5 50 Operational supply current4 MAX 500 9.5 UNITS V A mA Digital inputs CLK, DATA, STROBE VIH High level input voltage range 0.7xVDD VDD V VIL Low level input voltage range 0 0.3xVDD V 0.4 V Digital outputs LOCK VOL Output voltage LOW IO = 2mA VOH Output voltage HIGH IO = -2mA VDD-0.4 V Charge pump PHP (notes 3, 5):VDDA = 3V/IRx = 25A or VDDA = 5V/IRx = 62.5A, VPHP in range, unless otherwise specified |IRX| Setting current for RN or RF VPHP Output voltage range IPHP IPHP IPHP_PN PHP PN IPHP_I Output current7 25 4.5V < VDDA < 5.5V 62.5 0.7 A VDDA-0.8 IRN = -62.5A, VPHP = VDDA/2 (Note 7) 440 550 660 IRN = -25A, VPHP =VDDA/2 175 220 265 IRN = -62.5A1,7 Relative output current variation Output current matching 2.7V < VDDA < 5.5V 2 6 IRN = -25A, VPHP =VDDA/2 (Note 7) 50 IRN = -62.5A, VPHP = VDDA/2 65 Output leakage current (pump not active) VPHP =0.7 to VDDA-0.8 -20 0.1 20 IRF = -62.5A;FRD = 1 to 7 (Note 7) -625 -400 -250 IRF = -25A;FRD = 1 to 7 -250 -180 -100 V A % A nA Fractional compensation pump VRN = VDDA, VPHP = VDDA/2 IPHP_F PHP F 1995 Sep 1 Fractional compensation output current PHP vs FRD 754 nA Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 AC ELECTRICAL CHARACTERISTICS VDD = VDDA = 3V; TA = 25C; unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS Main divider guaranteed and tested on an automatic tester. Some performance parameters may be improved by using optimized layout. fRF_IN RF IN Input signal frequency VRF_IN Input sensitivity Pin = -20dBm, Direct coupled input 0 1.8 Pin = -20dBm, 1000pF input coupling fIN = 1800MHz GHz 1.8 -20 0 dBm Reference divider (VDD = VDDA = 3V or VDD = 3V / VDDA = 5V) fREF_IN REF IN Input signal frequency VREF_IN REF IN Input signal range range, AC coupled ZREF_IN REF IN Reference divider input impedance 2.7 < VDD and VDDA < 5.5V 25 2.7 < VDD and VDDA < 4.5V 30 2.7 < VDD and VDDA < 5.5V 500 2.7 < VDD and VDDA < 4.5V 300 MHz mVP-P PP 100 k 2 pF Serial interface fCLOCK Clock frequency 10 tSU 30 ns tH Hold time; CLOCK to DATA 30 ns Pulse width; CLOCK 30 tW tSW Pulse width; STROBE B, C, D, E words Pulse width; STROBE tSW P l width; Pulse id h STROBE ns 30 30 A word, PR = `01' ns (NM2x65)/Fvco +Tw A word, PR = `10' [NM2x65 + (NM3+1)x68]/Fvco +Tw A word, PR = `11' [NM2x65+(NM3+1)x68+(NM4+1)x73]/ Fvco +Tw A word, PR = `00' [NM2x65+(NM4+1)x73]/Fvco+Tw NOTES: 1. The relative output current variation is defined thus : 2. 3. 4. 5. 6. 7. 8. 9. MHz Set-up time: DATA to CLOCK, CLOCK to STROBE I OUT (I2 I1) 2 withV1=0.7V,V2=Vdda-0.8V I OUT I(I2 I1) FRD is the value of the fractional accumulator Monotonicity is guaranteed with CN = 0 to 255 Power supply current measured in loop Specification condition : CN = 255 The matching is defined by the sum of the P and the N pump for a given output voltage. Limited analog supply voltage to 4.5 to 5.5V For FIN <50MHz, low frequency operation requires DC coupling and a minimum input slew rate of 32V/s. Guaranteed by design 1995 Sep 1 755 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 CURRENT I2 I1 V1 V2 VOLTAGE I2 I1 SR01012 Figure 3. Relative Output Current Variation 10F 22nF CLOCK CLOCK DATA STROBE 10k 22nF RFIN+ 50 22nF RFIN- VCCP DATA TEST STROBE LOCK VSS RF RFIN+ RN RFIN- 50 22nF REFIN 50 10F 22nF VDD VDD TEST LOCK 150k 150k SA8015 VDDA VCCP PHP REFIN NC NC VSSA NC NC 1k VDDA 10F 22nF SR01013 Figure 4. Test Circuit AC TIMING CHARACTERISTICS tSU tH tW tSU 1/Fclock CLK DATA MSB LSB ADDRESS ENABLE tSW SR01014 Figure 5. Serial Input Timing Sequence 1995 Sep 1 756 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer For PR='00' Tstrobe_min FUNCTIONAL DESCRIPTION Serial input programming The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter ratios, DAC, selection and enable bits. The programming data is structured into 24- or 32-bit words; each word includes 1 or 4 address bits. Figure 5 shows the timing diagram of the serial input. When the STROBE=H, the clock is disabled and the data in the shift register remains stable. Depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 3 words must be sent: D,B, and A. Figure 6 and Table 1 show the format and the contents of each word. The E word is for testing purposes only. The E (test) word is reset when programming the D word. The data for CN and PR is strored by the B word in temporary registers. When the A word is loaded, the data of these temporary registers is loaded together with the main divider input. CN is only loaded from the temporary registers when a short 24-bit A0 word is issued. CN will be directly loaded by programming a long 32-bit A1 word. The flag LONG in the D word determines whether A0 (LONG=`0') or A1 (LONG=`1') format is applicable. The A word contains new data for the main divider. The input signal on REF_in is amplified to logic level by a single-ended CMOS input buffer, which accepts low level AC coupled input signals. This input stage is enabled by the EM bit. Disabling means that all currents in the input stage are switched off. The reference divider consists of a programmable divider by NR (NR=4 to 4095) followed by a three bit binary counter. The 2 bit SM register determines which of the 4 output pulses is selected as the phase detector input. Main Divider The differential inputs are amplified (to internal ECL logic levels) and provide excellent sensitivity (-20dBm at 1.8GHz) making the prescaler ideally suited to direct interface to a VCO as integrated on the Philips front-end devices including RF gain stage, VCO and mixer. The internal four modulus prescaler feedback loop FB controls the selection of the divide by ratios 64/65/68/73, and reduces the minimum system division ratio below the typical value required by standard dual modulus (64/65) devices. The A word is loaded only when a main divider synchronization signal is also active in order to avoid phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider. The signal is active while the NM1 divider is counting down from the programmed value. The new A word will be loaded after the NM1 divider output pulse will be sent to the main phase detector. The loading of the A word is disabled while the other dividers are counting up to their programmed values. Therefore, the new A word will be correctly loaded provided that the STROBE signal has been at an active high value for at least a minimum number of VCO cycles. 1 (NM2.65) T W F VCO For PR='10' Tstrobe_min 1 (NM2.65) (NM3 1) 68) T W F VCO The main divider consists of a 12 bit counter plus a sign bit. Depending on the serial input values NM1, NM2, NM3, NM4 and the prescaler select PR, the counter will select a prescaler ratio during a number of input cycles according to Tables 2 and 3. The loading of the work registers NM1, NM2, NM3, NM4 and PR is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as explainded in the Serial Input Programming section. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented with NF. The accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD='1'. Each time the accumulator overflows, the feedback to the prescaler will select on cycle using prescaler ratio R2 instead of R1. The mean division ratio over Q main divider will then be NQ=N+NF/Q 1 (NM2.65) (NM3 1) 68 (NM4 1) 73) T W F VCO 1995 Sep 1 This input stage is enabled when serial control bit EM='1'. Disabling means that all currents in the prescaler are switched off. For PR='11' Tstrobe_min Reference Divider Main divider synchronization For PR='01' Tstrobe_min 1 (NM2.65 (NM4 1) 73) T W F VCO SA8015 Programming a fraction means the prescaler with main divider will divide by N or N+1. The output of the main divider will be modulated with a fractional phase ripple. This phase ripple is proportional to the content of the fractional accumulator FRD, which is used for fractional current compensation. 757 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 INTERNAL REGISTERS Last in First in word MSB LSB NM2 A1 0 NF CN NM1 NM3 NM2 PR=01 NM2 A0 0 NF NM1 NM3 B 1 0 0 0 D 1 0 1 0 E 1 1 1 1 NM4 0 0 0 0 CN SM NR 0 0 0 T 1 T 0 NM2 0 0 E 0 0 0 M PR 01 PR F M O D L O N G 0 SR01015 Figure 6. Serial Bus Timing Diagram 1995 Sep 1 758 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 Table 1. Register Description SYMBOL BITS FUNCTION NM1 12 Number of main divider cycles when prescaler modulus=64 NM2 4 or 8 Number of main divider cycles when prescaler modulus=65 NM3 0 or 4 Number of main divider cycles when prescaler modulus=68 NM4 4 Number of main divider cycles when prescaler modulus=73 PR 2 Prescaler type in use PR="01": modulus 2 prescaler (64/65) PR="10": modulus 3 prescaler (64/65/68) PR="11": modulus 4 prescaler (64/65/68/73) PR="00": modulus 3 prescaler (64/65/73) NF 3 Fractional-N increment FMOD 1 Fractional-N modulus selection "1": modulo 8 "0": modulo5 LONG 1 A word format selection "0": 24 bit A0 format "1": 32 bit A1 format CN 8 Binary current setting factor for the chargepump EM 1 Enable bit. "1": synthesizer is ON SM 2 Reference divider output selection SM="00": No extra division on reference divider SM="01": Extra divide by 2 SM="10": Extra divide by 4 SM="11": Extra divide by 8 NR 12 Reference divider ratio Table 2. Prescaler Ratio The total division ration from prescaler to the phase detector may be expressed as: if PR= `01' N = (NM1 + 2) x 64 + NM2 x 65 if PR= `10' N = (NM1 + 2) x 64 + N2 x 65 + (NM3 + 1) x 68 if PR= `11' N = (NM1 + 2) x 64 + N2 x 65 + (NM3 + 1) x 68 + (NM4 + 1) x 73 if PR= `00' N = (NM1 + 2) x 64 + N2 x 65 + (NM4 + 1) x 73 When the fractional accumulator overflows, the divide ratio is increased by 1 Table 3. PR Modulus Bit capacity PR Modulus prescaler NM1 NM2 NM3 NM4 01 2 12 8 - - 10 3 12 4 4 - 11 4 12 4 4 4 00 4 12 8 - 4 1995 Sep 1 759 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 PHASE DETECTOR L VDDA "1" P D P-TYPE CHARGEPUMP Q REFin REFERENCE C R DIVIDER R PHP "1" VCOin D R N MAIN DIVIDER N-tTYPE C M CHARGEPUMP Q VSSA REFin L R M P N IPHP SR01016 Figure 7. Phase Detector Structure with Timing The phase detector is a two D-type flip-flop phase and frequency detector shown in Figure 7. The flip-flops are set by the negative edges of output signals of the dividers. The rising edge of the signal, L, will reset the flip-flops after both flip-flops have been set. Around zero phase error, this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive an on-chip chargepump. A source current from the chargepump indicates the VCO frequency will be increased; a sink current indicates the VCO frequency will be decreased. 1995 Sep 1 Current Settings The SA8015 has two current setting pins: RN and RF. The active chargepump current and the fractional compensation current are linearly dependent on the current connected between the current setting pin and VSSA. The typical value R (current setting resistor) can be calculated with the formula: R V DDA - 0.9 - 150 I R IR The current can be set to zero by connecting the corresponding pin to VDDA. All currents are off when the part is disabled through the EM bit of the serial interface. 760 Philips Semiconductors Objective specification 2GHz low voltage Fractional-N synthesizer SA8015 CHARGEPUMP OUTPUT AND FRACTIONAL COMPENSATION CURRENT REFERENCE R MAIN M DIVIDE RATIO N N N+1 N N+1 DETECTOR OUTPUT 2 4 1 3 0 ACCUMULATOR FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION mA OUTPUT ON PHP A PULSE LEVEL MODULATION SR01017 Figure 8. Waveforms for NF = 2, Fraction = 0.4 The chargepump on pin PHP is driven by the phase detector and the current value is determined by the current at pin RN and the CN DAC which is driven by a register of the serial input. The fractional compensation current is determined by the current at pin RF, the contents of the fractional accumulator FRD. The timing for the fractional compensation is derived from the reference divider. The current is on during one input reference cycle before and one cycle after the output signal to the phase comparator. Figure 8 shows the waveform for a typical case. Lock Detect The output LOCK is H when the phase detector indicates a lock condition. The lock condition is defined as a phase difference of less than +1 cycle on the reference input REFin. The lock condition is also fulfilled when the synthesizer is disabled. Test Modes The lock ouput is selectable as FREF, FMAIN and lock. Bits T1 and T0 of the E word control the selection. IPHP = INOMINAL + IFRACTIONAL_COMPENSATION INOMINAL = CN * IRN/32 : charge pump current T1=0 and T0=0 or the E register is not programmed : lock output is configured as lock indicator. IFRACTIONAL_COMPENSATION = FRD * IRF/128 : fractional compensation current. T1=0 and T0=1, the lock output gives the output of the reference divider Figure 8 shows that for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. This means that the current setting T1=1 and T0=1, the lock output gives the output of the main divider. on the input RN, RF is approximately The E register is reset to 0 anytime the D word is programmed. The test input pin (Pin 19) is a buffured logic input which is exclusively ORed with the output of the prescaler. The output of the XOR gate is the input to the MAIN divider. The Test pin must be connected to VDD during normal operation as a synthesizer. This pin can be used as an input for verifying the divide ratio of the main divider; while in this condition the input to the prescaler, RFin, may be connected to VCCP through a 10k resistor in order to place the prescaler output into a known state. (Q F VCO ) I RN I RF (3 CN F REF) where : Q=fractional-N modulus FVCO = input frequency of the prescaler FREF = input frequency of the reference divider. 1995 Sep 1 761